/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Assembly Writer Source Fragment                                            *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

/// getMnemonic - This method is automatically generated by tablegen
/// from the instruction set description.
std::pair<const char *, uint64_t> MipsInstPrinter::getMnemonic(const MCInst *MI) {

#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
  static const char AsmStrs[] = {
  /* 0 */ "dmfc0\t\0"
  /* 7 */ "dmfgc0\t\0"
  /* 15 */ "mfhgc0\t\0"
  /* 23 */ "mthgc0\t\0"
  /* 31 */ "dmtgc0\t\0"
  /* 39 */ "mfhc0\t\0"
  /* 46 */ "mthc0\t\0"
  /* 53 */ "dmtc0\t\0"
  /* 60 */ "vmm0\t\0"
  /* 66 */ "mtm0\t\0"
  /* 72 */ "mtp0\t\0"
  /* 78 */ "bbit0\t\0"
  /* 85 */ "ldc1\t\0"
  /* 91 */ "sdc1\t\0"
  /* 97 */ "cfc1\t\0"
  /* 103 */ "dmfc1\t\0"
  /* 110 */ "mfhc1\t\0"
  /* 117 */ "mthc1\t\0"
  /* 124 */ "ctc1\t\0"
  /* 130 */ "dmtc1\t\0"
  /* 137 */ "lwc1\t\0"
  /* 143 */ "swc1\t\0"
  /* 149 */ "ldxc1\t\0"
  /* 156 */ "sdxc1\t\0"
  /* 163 */ "luxc1\t\0"
  /* 170 */ "suxc1\t\0"
  /* 177 */ "lwxc1\t\0"
  /* 184 */ "swxc1\t\0"
  /* 191 */ "mtm1\t\0"
  /* 197 */ "mtp1\t\0"
  /* 203 */ "bbit1\t\0"
  /* 210 */ "bbit032\t\0"
  /* 219 */ "bbit132\t\0"
  /* 228 */ "dsra32\t\0"
  /* 236 */ "bposge32\t\0"
  /* 246 */ "dsll32\t\0"
  /* 254 */ "dsrl32\t\0"
  /* 262 */ "lwm32\t\0"
  /* 269 */ "swm32\t\0"
  /* 276 */ "drotr32\t\0"
  /* 285 */ "cins32\t\0"
  /* 293 */ "exts32\t\0"
  /* 301 */ "ldc2\t\0"
  /* 307 */ "sdc2\t\0"
  /* 313 */ "cfc2\t\0"
  /* 319 */ "dmfc2\t\0"
  /* 326 */ "mfhc2\t\0"
  /* 333 */ "mthc2\t\0"
  /* 340 */ "ctc2\t\0"
  /* 346 */ "dmtc2\t\0"
  /* 353 */ "lwc2\t\0"
  /* 359 */ "swc2\t\0"
  /* 365 */ "mtm2\t\0"
  /* 371 */ "mtp2\t\0"
  /* 377 */ "addiur2\t\0"
  /* 386 */ "ldc3\t\0"
  /* 392 */ "sdc3\t\0"
  /* 398 */ "lwc3\t\0"
  /* 404 */ "swc3\t\0"
  /* 410 */ "addius5\t\0"
  /* 419 */ "sb16\t\0"
  /* 425 */ "bc16\t\0"
  /* 431 */ "jrc16\t\0"
  /* 438 */ "bnezc16\t\0"
  /* 447 */ "beqzc16\t\0"
  /* 456 */ "and16\t\0"
  /* 463 */ "move16\t\0"
  /* 471 */ "sh16\t\0"
  /* 477 */ "andi16\t\0"
  /* 485 */ "mfhi16\t\0"
  /* 493 */ "li16\t\0"
  /* 499 */ "break16\t\0"
  /* 508 */ "sll16\t\0"
  /* 515 */ "srl16\t\0"
  /* 522 */ "lwm16\t\0"
  /* 529 */ "swm16\t\0"
  /* 536 */ "mflo16\t\0"
  /* 544 */ "sdbbp16\t\0"
  /* 553 */ "jr16\t\0"
  /* 559 */ "xor16\t\0"
  /* 566 */ "jalrs16\t\0"
  /* 575 */ "not16\t\0"
  /* 582 */ "lbu16\t\0"
  /* 589 */ "subu16\t\0"
  /* 597 */ "addu16\t\0"
  /* 605 */ "lhu16\t\0"
  /* 612 */ "lw16\t\0"
  /* 618 */ "sw16\t\0"
  /* 624 */ "bnez16\t\0"
  /* 632 */ "beqz16\t\0"
  /* 640 */ "saa\t\0"
  /* 645 */ "preceu.ph.qbla\t\0"
  /* 661 */ "precequ.ph.qbla\t\0"
  /* 678 */ "dla\t\0"
  /* 683 */ "preceu.ph.qbra\t\0"
  /* 699 */ "precequ.ph.qbra\t\0"
  /* 716 */ "dsra\t\0"
  /* 722 */ "dlsa\t\0"
  /* 728 */ "cfcmsa\t\0"
  /* 736 */ "ctcmsa\t\0"
  /* 744 */ "add_a.b\t\0"
  /* 753 */ "min_a.b\t\0"
  /* 762 */ "adds_a.b\t\0"
  /* 772 */ "max_a.b\t\0"
  /* 781 */ "sra.b\t\0"
  /* 788 */ "nloc.b\t\0"
  /* 796 */ "nlzc.b\t\0"
  /* 804 */ "sld.b\t\0"
  /* 811 */ "pckod.b\t\0"
  /* 820 */ "ilvod.b\t\0"
  /* 829 */ "insve.b\t\0"
  /* 838 */ "vshf.b\t\0"
  /* 846 */ "bneg.b\t\0"
  /* 854 */ "srai.b\t\0"
  /* 862 */ "sldi.b\t\0"
  /* 870 */ "andi.b\t\0"
  /* 878 */ "bnegi.b\t\0"
  /* 887 */ "bseli.b\t\0"
  /* 896 */ "slli.b\t\0"
  /* 904 */ "srli.b\t\0"
  /* 912 */ "binsli.b\t\0"
  /* 922 */ "ceqi.b\t\0"
  /* 930 */ "srari.b\t\0"
  /* 939 */ "bclri.b\t\0"
  /* 948 */ "srlri.b\t\0"
  /* 957 */ "nori.b\t\0"
  /* 965 */ "xori.b\t\0"
  /* 973 */ "binsri.b\t\0"
  /* 983 */ "splati.b\t\0"
  /* 993 */ "bseti.b\t\0"
  /* 1002 */ "subvi.b\t\0"
  /* 1011 */ "addvi.b\t\0"
  /* 1020 */ "bmzi.b\t\0"
  /* 1028 */ "bmnzi.b\t\0"
  /* 1037 */ "fill.b\t\0"
  /* 1045 */ "sll.b\t\0"
  /* 1052 */ "srl.b\t\0"
  /* 1059 */ "binsl.b\t\0"
  /* 1068 */ "ilvl.b\t\0"
  /* 1076 */ "ceq.b\t\0"
  /* 1083 */ "srar.b\t\0"
  /* 1091 */ "bclr.b\t\0"
  /* 1099 */ "srlr.b\t\0"
  /* 1107 */ "binsr.b\t\0"
  /* 1116 */ "ilvr.b\t\0"
  /* 1124 */ "asub_s.b\t\0"
  /* 1134 */ "mod_s.b\t\0"
  /* 1143 */ "cle_s.b\t\0"
  /* 1152 */ "ave_s.b\t\0"
  /* 1161 */ "clei_s.b\t\0"
  /* 1171 */ "mini_s.b\t\0"
  /* 1181 */ "clti_s.b\t\0"
  /* 1191 */ "maxi_s.b\t\0"
  /* 1201 */ "min_s.b\t\0"
  /* 1210 */ "aver_s.b\t\0"
  /* 1220 */ "subs_s.b\t\0"
  /* 1230 */ "adds_s.b\t\0"
  /* 1240 */ "sat_s.b\t\0"
  /* 1249 */ "clt_s.b\t\0"
  /* 1258 */ "subsuu_s.b\t\0"
  /* 1270 */ "div_s.b\t\0"
  /* 1279 */ "max_s.b\t\0"
  /* 1288 */ "copy_s.b\t\0"
  /* 1298 */ "splat.b\t\0"
  /* 1307 */ "bset.b\t\0"
  /* 1315 */ "pcnt.b\t\0"
  /* 1323 */ "insert.b\t\0"
  /* 1333 */ "st.b\t\0"
  /* 1339 */ "asub_u.b\t\0"
  /* 1349 */ "mod_u.b\t\0"
  /* 1358 */ "cle_u.b\t\0"
  /* 1367 */ "ave_u.b\t\0"
  /* 1376 */ "clei_u.b\t\0"
  /* 1386 */ "mini_u.b\t\0"
  /* 1396 */ "clti_u.b\t\0"
  /* 1406 */ "maxi_u.b\t\0"
  /* 1416 */ "min_u.b\t\0"
  /* 1425 */ "aver_u.b\t\0"
  /* 1435 */ "subs_u.b\t\0"
  /* 1445 */ "adds_u.b\t\0"
  /* 1455 */ "subsus_u.b\t\0"
  /* 1467 */ "sat_u.b\t\0"
  /* 1476 */ "clt_u.b\t\0"
  /* 1485 */ "div_u.b\t\0"
  /* 1494 */ "max_u.b\t\0"
  /* 1503 */ "copy_u.b\t\0"
  /* 1513 */ "msubv.b\t\0"
  /* 1522 */ "maddv.b\t\0"
  /* 1531 */ "pckev.b\t\0"
  /* 1540 */ "ilvev.b\t\0"
  /* 1549 */ "mulv.b\t\0"
  /* 1557 */ "bz.b\t\0"
  /* 1563 */ "bnz.b\t\0"
  /* 1570 */ "crc32b\t\0"
  /* 1578 */ "crc32cb\t\0"
  /* 1587 */ "seb\t\0"
  /* 1592 */ "jalrc.hb\t\0"
  /* 1602 */ "jr.hb\t\0"
  /* 1609 */ "jalr.hb\t\0"
  /* 1618 */ "lb\t\0"
  /* 1622 */ "shra.qb\t\0"
  /* 1631 */ "cmpgdu.le.qb\t\0"
  /* 1645 */ "cmpgu.le.qb\t\0"
  /* 1658 */ "cmpu.le.qb\t\0"
  /* 1670 */ "subuh.qb\t\0"
  /* 1680 */ "adduh.qb\t\0"
  /* 1690 */ "pick.qb\t\0"
  /* 1699 */ "shll.qb\t\0"
  /* 1708 */ "repl.qb\t\0"
  /* 1717 */ "shrl.qb\t\0"
  /* 1726 */ "cmpgdu.eq.qb\t\0"
  /* 1740 */ "cmpgu.eq.qb\t\0"
  /* 1753 */ "cmpu.eq.qb\t\0"
  /* 1765 */ "shra_r.qb\t\0"
  /* 1776 */ "subuh_r.qb\t\0"
  /* 1788 */ "adduh_r.qb\t\0"
  /* 1800 */ "shrav_r.qb\t\0"
  /* 1812 */ "absq_s.qb\t\0"
  /* 1823 */ "subu_s.qb\t\0"
  /* 1834 */ "addu_s.qb\t\0"
  /* 1845 */ "cmpgdu.lt.qb\t\0"
  /* 1859 */ "cmpgu.lt.qb\t\0"
  /* 1872 */ "cmpu.lt.qb\t\0"
  /* 1884 */ "subu.qb\t\0"
  /* 1893 */ "addu.qb\t\0"
  /* 1902 */ "shrav.qb\t\0"
  /* 1912 */ "shllv.qb\t\0"
  /* 1922 */ "replv.qb\t\0"
  /* 1932 */ "shrlv.qb\t\0"
  /* 1942 */ "raddu.w.qb\t\0"
  /* 1954 */ "sb\t\0"
  /* 1958 */ "modsub\t\0"
  /* 1966 */ "msub\t\0"
  /* 1972 */ "bposge32c\t\0"
  /* 1983 */ "bc\t\0"
  /* 1987 */ "bgec\t\0"
  /* 1993 */ "bnec\t\0"
  /* 1999 */ "jic\t\0"
  /* 2004 */ "balc\t\0"
  /* 2010 */ "jialc\t\0"
  /* 2017 */ "bgezalc\t\0"
  /* 2026 */ "blezalc\t\0"
  /* 2035 */ "bnezalc\t\0"
  /* 2044 */ "beqzalc\t\0"
  /* 2053 */ "bgtzalc\t\0"
  /* 2062 */ "bltzalc\t\0"
  /* 2071 */ "sync\t\0"
  /* 2077 */ "ldpc\t\0"
  /* 2083 */ "auipc\t\0"
  /* 2090 */ "aluipc\t\0"
  /* 2098 */ "addiupc\t\0"
  /* 2107 */ "lwupc\t\0"
  /* 2114 */ "lwpc\t\0"
  /* 2120 */ "beqc\t\0"
  /* 2126 */ "jrc\t\0"
  /* 2131 */ "jalrc\t\0"
  /* 2138 */ "addsc\t\0"
  /* 2145 */ "bltc\t\0"
  /* 2151 */ "bgeuc\t\0"
  /* 2158 */ "bltuc\t\0"
  /* 2165 */ "bnvc\t\0"
  /* 2171 */ "bovc\t\0"
  /* 2177 */ "addwc\t\0"
  /* 2184 */ "bgezc\t\0"
  /* 2191 */ "blezc\t\0"
  /* 2198 */ "bc1nezc\t\0"
  /* 2207 */ "bc2nezc\t\0"
  /* 2216 */ "bnezc\t\0"
  /* 2223 */ "bc1eqzc\t\0"
  /* 2232 */ "bc2eqzc\t\0"
  /* 2241 */ "beqzc\t\0"
  /* 2248 */ "bgtzc\t\0"
  /* 2255 */ "bltzc\t\0"
  /* 2262 */ "flog2.d\t\0"
  /* 2271 */ "fexp2.d\t\0"
  /* 2280 */ "add_a.d\t\0"
  /* 2289 */ "fmin_a.d\t\0"
  /* 2299 */ "adds_a.d\t\0"
  /* 2309 */ "fmax_a.d\t\0"
  /* 2319 */ "mina.d\t\0"
  /* 2327 */ "sra.d\t\0"
  /* 2334 */ "maxa.d\t\0"
  /* 2342 */ "fsub.d\t\0"
  /* 2350 */ "fmsub.d\t\0"
  /* 2359 */ "nmsub.d\t\0"
  /* 2368 */ "nloc.d\t\0"
  /* 2376 */ "nlzc.d\t\0"
  /* 2384 */ "fadd.d\t\0"
  /* 2392 */ "fmadd.d\t\0"
  /* 2401 */ "nmadd.d\t\0"
  /* 2410 */ "sld.d\t\0"
  /* 2417 */ "pckod.d\t\0"
  /* 2426 */ "ilvod.d\t\0"
  /* 2435 */ "c.nge.d\t\0"
  /* 2444 */ "c.le.d\t\0"
  /* 2452 */ "cmp.le.d\t\0"
  /* 2462 */ "fcle.d\t\0"
  /* 2470 */ "c.ngle.d\t\0"
  /* 2480 */ "c.ole.d\t\0"
  /* 2489 */ "cmp.sle.d\t\0"
  /* 2500 */ "fsle.d\t\0"
  /* 2508 */ "c.ule.d\t\0"
  /* 2517 */ "cmp.ule.d\t\0"
  /* 2528 */ "fcule.d\t\0"
  /* 2537 */ "cmp.sule.d\t\0"
  /* 2549 */ "fsule.d\t\0"
  /* 2558 */ "fcne.d\t\0"
  /* 2566 */ "fsne.d\t\0"
  /* 2574 */ "fcune.d\t\0"
  /* 2583 */ "fsune.d\t\0"
  /* 2592 */ "insve.d\t\0"
  /* 2601 */ "c.f.d\t\0"
  /* 2608 */ "cmp.af.d\t\0"
  /* 2618 */ "fcaf.d\t\0"
  /* 2626 */ "cmp.saf.d\t\0"
  /* 2637 */ "fsaf.d\t\0"
  /* 2645 */ "msubf.d\t\0"
  /* 2654 */ "maddf.d\t\0"
  /* 2663 */ "vshf.d\t\0"
  /* 2671 */ "c.sf.d\t\0"
  /* 2679 */ "movf.d\t\0"
  /* 2687 */ "bneg.d\t\0"
  /* 2695 */ "srai.d\t\0"
  /* 2703 */ "sldi.d\t\0"
  /* 2711 */ "bnegi.d\t\0"
  /* 2720 */ "slli.d\t\0"
  /* 2728 */ "srli.d\t\0"
  /* 2736 */ "binsli.d\t\0"
  /* 2746 */ "ceqi.d\t\0"
  /* 2754 */ "srari.d\t\0"
  /* 2763 */ "bclri.d\t\0"
  /* 2772 */ "srlri.d\t\0"
  /* 2781 */ "binsri.d\t\0"
  /* 2791 */ "splati.d\t\0"
  /* 2801 */ "bseti.d\t\0"
  /* 2810 */ "subvi.d\t\0"
  /* 2819 */ "addvi.d\t\0"
  /* 2828 */ "trunc.l.d\t\0"
  /* 2839 */ "round.l.d\t\0"
  /* 2850 */ "ceil.l.d\t\0"
  /* 2860 */ "floor.l.d\t\0"
  /* 2871 */ "cvt.l.d\t\0"
  /* 2880 */ "sel.d\t\0"
  /* 2887 */ "c.ngl.d\t\0"
  /* 2896 */ "fill.d\t\0"
  /* 2904 */ "sll.d\t\0"
  /* 2911 */ "fexupl.d\t\0"
  /* 2921 */ "ffql.d\t\0"
  /* 2929 */ "srl.d\t\0"
  /* 2936 */ "binsl.d\t\0"
  /* 2945 */ "fmul.d\t\0"
  /* 2953 */ "ilvl.d\t\0"
  /* 2961 */ "fmin.d\t\0"
  /* 2969 */ "c.un.d\t\0"
  /* 2977 */ "cmp.un.d\t\0"
  /* 2987 */ "fcun.d\t\0"
  /* 2995 */ "cmp.sun.d\t\0"
  /* 3006 */ "fsun.d\t\0"
  /* 3014 */ "movn.d\t\0"
  /* 3022 */ "frcp.d\t\0"
  /* 3030 */ "recip.d\t\0"
  /* 3039 */ "c.eq.d\t\0"
  /* 3047 */ "cmp.eq.d\t\0"
  /* 3057 */ "fceq.d\t\0"
  /* 3065 */ "c.seq.d\t\0"
  /* 3074 */ "cmp.seq.d\t\0"
  /* 3085 */ "fseq.d\t\0"
  /* 3093 */ "c.ueq.d\t\0"
  /* 3102 */ "cmp.ueq.d\t\0"
  /* 3113 */ "fcueq.d\t\0"
  /* 3122 */ "cmp.sueq.d\t\0"
  /* 3134 */ "fsueq.d\t\0"
  /* 3143 */ "srar.d\t\0"
  /* 3151 */ "bclr.d\t\0"
  /* 3159 */ "srlr.d\t\0"
  /* 3167 */ "fcor.d\t\0"
  /* 3175 */ "fsor.d\t\0"
  /* 3183 */ "fexupr.d\t\0"
  /* 3193 */ "ffqr.d\t\0"
  /* 3201 */ "binsr.d\t\0"
  /* 3210 */ "ilvr.d\t\0"
  /* 3218 */ "cvt.s.d\t\0"
  /* 3227 */ "asub_s.d\t\0"
  /* 3237 */ "hsub_s.d\t\0"
  /* 3247 */ "dpsub_s.d\t\0"
  /* 3258 */ "ftrunc_s.d\t\0"
  /* 3270 */ "hadd_s.d\t\0"
  /* 3280 */ "dpadd_s.d\t\0"
  /* 3291 */ "mod_s.d\t\0"
  /* 3300 */ "cle_s.d\t\0"
  /* 3309 */ "ave_s.d\t\0"
  /* 3318 */ "clei_s.d\t\0"
  /* 3328 */ "mini_s.d\t\0"
  /* 3338 */ "clti_s.d\t\0"
  /* 3348 */ "maxi_s.d\t\0"
  /* 3358 */ "min_s.d\t\0"
  /* 3367 */ "dotp_s.d\t\0"
  /* 3377 */ "aver_s.d\t\0"
  /* 3387 */ "subs_s.d\t\0"
  /* 3397 */ "adds_s.d\t\0"
  /* 3407 */ "sat_s.d\t\0"
  /* 3416 */ "clt_s.d\t\0"
  /* 3425 */ "ffint_s.d\t\0"
  /* 3436 */ "ftint_s.d\t\0"
  /* 3447 */ "subsuu_s.d\t\0"
  /* 3459 */ "div_s.d\t\0"
  /* 3468 */ "max_s.d\t\0"
  /* 3477 */ "copy_s.d\t\0"
  /* 3487 */ "abs.d\t\0"
  /* 3494 */ "fclass.d\t\0"
  /* 3504 */ "splat.d\t\0"
  /* 3513 */ "bset.d\t\0"
  /* 3521 */ "c.ngt.d\t\0"
  /* 3530 */ "c.lt.d\t\0"
  /* 3538 */ "cmp.lt.d\t\0"
  /* 3548 */ "fclt.d\t\0"
  /* 3556 */ "c.olt.d\t\0"
  /* 3565 */ "cmp.slt.d\t\0"
  /* 3576 */ "fslt.d\t\0"
  /* 3584 */ "c.ult.d\t\0"
  /* 3593 */ "cmp.ult.d\t\0"
  /* 3604 */ "fcult.d\t\0"
  /* 3613 */ "cmp.sult.d\t\0"
  /* 3625 */ "fsult.d\t\0"
  /* 3634 */ "pcnt.d\t\0"
  /* 3642 */ "frint.d\t\0"
  /* 3651 */ "insert.d\t\0"
  /* 3661 */ "fsqrt.d\t\0"
  /* 3670 */ "frsqrt.d\t\0"
  /* 3680 */ "st.d\t\0"
  /* 3686 */ "movt.d\t\0"
  /* 3694 */ "asub_u.d\t\0"
  /* 3704 */ "hsub_u.d\t\0"
  /* 3714 */ "dpsub_u.d\t\0"
  /* 3725 */ "ftrunc_u.d\t\0"
  /* 3737 */ "hadd_u.d\t\0"
  /* 3747 */ "dpadd_u.d\t\0"
  /* 3758 */ "mod_u.d\t\0"
  /* 3767 */ "cle_u.d\t\0"
  /* 3776 */ "ave_u.d\t\0"
  /* 3785 */ "clei_u.d\t\0"
  /* 3795 */ "mini_u.d\t\0"
  /* 3805 */ "clti_u.d\t\0"
  /* 3815 */ "maxi_u.d\t\0"
  /* 3825 */ "min_u.d\t\0"
  /* 3834 */ "dotp_u.d\t\0"
  /* 3844 */ "aver_u.d\t\0"
  /* 3854 */ "subs_u.d\t\0"
  /* 3864 */ "adds_u.d\t\0"
  /* 3874 */ "subsus_u.d\t\0"
  /* 3886 */ "sat_u.d\t\0"
  /* 3895 */ "clt_u.d\t\0"
  /* 3904 */ "ffint_u.d\t\0"
  /* 3915 */ "ftint_u.d\t\0"
  /* 3926 */ "div_u.d\t\0"
  /* 3935 */ "max_u.d\t\0"
  /* 3944 */ "msubv.d\t\0"
  /* 3953 */ "maddv.d\t\0"
  /* 3962 */ "pckev.d\t\0"
  /* 3971 */ "ilvev.d\t\0"
  /* 3980 */ "fdiv.d\t\0"
  /* 3988 */ "mulv.d\t\0"
  /* 3996 */ "mov.d\t\0"
  /* 4003 */ "trunc.w.d\t\0"
  /* 4014 */ "round.w.d\t\0"
  /* 4025 */ "ceil.w.d\t\0"
  /* 4035 */ "floor.w.d\t\0"
  /* 4046 */ "cvt.w.d\t\0"
  /* 4055 */ "fmax.d\t\0"
  /* 4063 */ "bz.d\t\0"
  /* 4069 */ "selnez.d\t\0"
  /* 4079 */ "bnz.d\t\0"
  /* 4086 */ "seleqz.d\t\0"
  /* 4096 */ "movz.d\t\0"
  /* 4104 */ "crc32d\t\0"
  /* 4112 */ "saad\t\0"
  /* 4118 */ "crc32cd\t\0"
  /* 4127 */ "scd\t\0"
  /* 4132 */ "dadd\t\0"
  /* 4138 */ "madd\t\0"
  /* 4144 */ "dshd\t\0"
  /* 4150 */ "yield\t\0"
  /* 4157 */ "lld\t\0"
  /* 4162 */ "and\t\0"
  /* 4167 */ "prepend\t\0"
  /* 4176 */ "append\t\0"
  /* 4184 */ "dmod\t\0"
  /* 4190 */ "sd\t\0"
  /* 4194 */ "lbe\t\0"
  /* 4199 */ "sbe\t\0"
  /* 4204 */ "sce\t\0"
  /* 4209 */ "cachee\t\0"
  /* 4217 */ "prefe\t\0"
  /* 4224 */ "bge\t\0"
  /* 4229 */ "sge\t\0"
  /* 4234 */ "tge\t\0"
  /* 4239 */ "cache\t\0"
  /* 4246 */ "lhe\t\0"
  /* 4251 */ "she\t\0"
  /* 4256 */ "sigrie\t\0"
  /* 4264 */ "ble\t\0"
  /* 4269 */ "lle\t\0"
  /* 4274 */ "sle\t\0"
  /* 4279 */ "lwle\t\0"
  /* 4285 */ "swle\t\0"
  /* 4291 */ "bne\t\0"
  /* 4296 */ "sne\t\0"
  /* 4301 */ "tne\t\0"
  /* 4306 */ "dvpe\t\0"
  /* 4312 */ "evpe\t\0"
  /* 4318 */ "lwre\t\0"
  /* 4324 */ "swre\t\0"
  /* 4330 */ "lbue\t\0"
  /* 4336 */ "lhue\t\0"
  /* 4342 */ "move\t\0"
  /* 4348 */ "lwe\t\0"
  /* 4353 */ "swe\t\0"
  /* 4358 */ "bc1f\t\0"
  /* 4364 */ "pref\t\0"
  /* 4370 */ "movf\t\0"
  /* 4376 */ "neg\t\0"
  /* 4381 */ "add_a.h\t\0"
  /* 4390 */ "min_a.h\t\0"
  /* 4399 */ "adds_a.h\t\0"
  /* 4409 */ "max_a.h\t\0"
  /* 4418 */ "sra.h\t\0"
  /* 4425 */ "nloc.h\t\0"
  /* 4433 */ "nlzc.h\t\0"
  /* 4441 */ "sld.h\t\0"
  /* 4448 */ "pckod.h\t\0"
  /* 4457 */ "ilvod.h\t\0"
  /* 4466 */ "insve.h\t\0"
  /* 4475 */ "vshf.h\t\0"
  /* 4483 */ "bneg.h\t\0"
  /* 4491 */ "srai.h\t\0"
  /* 4499 */ "sldi.h\t\0"
  /* 4507 */ "bnegi.h\t\0"
  /* 4516 */ "slli.h\t\0"
  /* 4524 */ "srli.h\t\0"
  /* 4532 */ "binsli.h\t\0"
  /* 4542 */ "ceqi.h\t\0"
  /* 4550 */ "srari.h\t\0"
  /* 4559 */ "bclri.h\t\0"
  /* 4568 */ "srlri.h\t\0"
  /* 4577 */ "binsri.h\t\0"
  /* 4587 */ "splati.h\t\0"
  /* 4597 */ "bseti.h\t\0"
  /* 4606 */ "subvi.h\t\0"
  /* 4615 */ "addvi.h\t\0"
  /* 4624 */ "fill.h\t\0"
  /* 4632 */ "sll.h\t\0"
  /* 4639 */ "srl.h\t\0"
  /* 4646 */ "binsl.h\t\0"
  /* 4655 */ "ilvl.h\t\0"
  /* 4663 */ "fexdo.h\t\0"
  /* 4672 */ "msub_q.h\t\0"
  /* 4682 */ "madd_q.h\t\0"
  /* 4692 */ "mul_q.h\t\0"
  /* 4701 */ "msubr_q.h\t\0"
  /* 4712 */ "maddr_q.h\t\0"
  /* 4723 */ "mulr_q.h\t\0"
  /* 4733 */ "ceq.h\t\0"
  /* 4740 */ "ftq.h\t\0"
  /* 4747 */ "srar.h\t\0"
  /* 4755 */ "bclr.h\t\0"
  /* 4763 */ "srlr.h\t\0"
  /* 4771 */ "binsr.h\t\0"
  /* 4780 */ "ilvr.h\t\0"
  /* 4788 */ "asub_s.h\t\0"
  /* 4798 */ "hsub_s.h\t\0"
  /* 4808 */ "dpsub_s.h\t\0"
  /* 4819 */ "hadd_s.h\t\0"
  /* 4829 */ "dpadd_s.h\t\0"
  /* 4840 */ "mod_s.h\t\0"
  /* 4849 */ "cle_s.h\t\0"
  /* 4858 */ "ave_s.h\t\0"
  /* 4867 */ "clei_s.h\t\0"
  /* 4877 */ "mini_s.h\t\0"
  /* 4887 */ "clti_s.h\t\0"
  /* 4897 */ "maxi_s.h\t\0"
  /* 4907 */ "min_s.h\t\0"
  /* 4916 */ "dotp_s.h\t\0"
  /* 4926 */ "aver_s.h\t\0"
  /* 4936 */ "extr_s.h\t\0"
  /* 4946 */ "subs_s.h\t\0"
  /* 4956 */ "adds_s.h\t\0"
  /* 4966 */ "sat_s.h\t\0"
  /* 4975 */ "clt_s.h\t\0"
  /* 4984 */ "subsuu_s.h\t\0"
  /* 4996 */ "div_s.h\t\0"
  /* 5005 */ "extrv_s.h\t\0"
  /* 5016 */ "max_s.h\t\0"
  /* 5025 */ "copy_s.h\t\0"
  /* 5035 */ "splat.h\t\0"
  /* 5044 */ "bset.h\t\0"
  /* 5052 */ "pcnt.h\t\0"
  /* 5060 */ "insert.h\t\0"
  /* 5070 */ "st.h\t\0"
  /* 5076 */ "asub_u.h\t\0"
  /* 5086 */ "hsub_u.h\t\0"
  /* 5096 */ "dpsub_u.h\t\0"
  /* 5107 */ "hadd_u.h\t\0"
  /* 5117 */ "dpadd_u.h\t\0"
  /* 5128 */ "mod_u.h\t\0"
  /* 5137 */ "cle_u.h\t\0"
  /* 5146 */ "ave_u.h\t\0"
  /* 5155 */ "clei_u.h\t\0"
  /* 5165 */ "mini_u.h\t\0"
  /* 5175 */ "clti_u.h\t\0"
  /* 5185 */ "maxi_u.h\t\0"
  /* 5195 */ "min_u.h\t\0"
  /* 5204 */ "dotp_u.h\t\0"
  /* 5214 */ "aver_u.h\t\0"
  /* 5224 */ "subs_u.h\t\0"
  /* 5234 */ "adds_u.h\t\0"
  /* 5244 */ "subsus_u.h\t\0"
  /* 5256 */ "sat_u.h\t\0"
  /* 5265 */ "clt_u.h\t\0"
  /* 5274 */ "div_u.h\t\0"
  /* 5283 */ "max_u.h\t\0"
  /* 5292 */ "copy_u.h\t\0"
  /* 5302 */ "msubv.h\t\0"
  /* 5311 */ "maddv.h\t\0"
  /* 5320 */ "pckev.h\t\0"
  /* 5329 */ "ilvev.h\t\0"
  /* 5338 */ "mulv.h\t\0"
  /* 5346 */ "bz.h\t\0"
  /* 5352 */ "bnz.h\t\0"
  /* 5359 */ "crc32h\t\0"
  /* 5367 */ "dsbh\t\0"
  /* 5373 */ "wsbh\t\0"
  /* 5379 */ "crc32ch\t\0"
  /* 5388 */ "seh\t\0"
  /* 5393 */ "ulh\t\0"
  /* 5398 */ "shra.ph\t\0"
  /* 5407 */ "precrq.qb.ph\t\0"
  /* 5421 */ "precr.qb.ph\t\0"
  /* 5434 */ "precrqu_s.qb.ph\t\0"
  /* 5451 */ "cmp.le.ph\t\0"
  /* 5462 */ "subqh.ph\t\0"
  /* 5472 */ "addqh.ph\t\0"
  /* 5482 */ "pick.ph\t\0"
  /* 5491 */ "shll.ph\t\0"
  /* 5500 */ "repl.ph\t\0"
  /* 5509 */ "shrl.ph\t\0"
  /* 5518 */ "packrl.ph\t\0"
  /* 5529 */ "mul.ph\t\0"
  /* 5537 */ "subq.ph\t\0"
  /* 5546 */ "addq.ph\t\0"
  /* 5555 */ "cmp.eq.ph\t\0"
  /* 5566 */ "shra_r.ph\t\0"
  /* 5577 */ "subqh_r.ph\t\0"
  /* 5589 */ "addqh_r.ph\t\0"
  /* 5601 */ "shrav_r.ph\t\0"
  /* 5613 */ "shll_s.ph\t\0"
  /* 5624 */ "mul_s.ph\t\0"
  /* 5634 */ "subq_s.ph\t\0"
  /* 5645 */ "addq_s.ph\t\0"
  /* 5656 */ "mulq_s.ph\t\0"
  /* 5667 */ "absq_s.ph\t\0"
  /* 5678 */ "subu_s.ph\t\0"
  /* 5689 */ "addu_s.ph\t\0"
  /* 5700 */ "shllv_s.ph\t\0"
  /* 5712 */ "mulq_rs.ph\t\0"
  /* 5724 */ "cmp.lt.ph\t\0"
  /* 5735 */ "subu.ph\t\0"
  /* 5744 */ "addu.ph\t\0"
  /* 5753 */ "shrav.ph\t\0"
  /* 5763 */ "shllv.ph\t\0"
  /* 5773 */ "replv.ph\t\0"
  /* 5783 */ "shrlv.ph\t\0"
  /* 5793 */ "dpa.w.ph\t\0"
  /* 5803 */ "dpaqx_sa.w.ph\t\0"
  /* 5818 */ "dpsqx_sa.w.ph\t\0"
  /* 5833 */ "mulsa.w.ph\t\0"
  /* 5845 */ "dpaq_s.w.ph\t\0"
  /* 5858 */ "mulsaq_s.w.ph\t\0"
  /* 5873 */ "dpsq_s.w.ph\t\0"
  /* 5886 */ "dpaqx_s.w.ph\t\0"
  /* 5900 */ "dpsqx_s.w.ph\t\0"
  /* 5914 */ "dps.w.ph\t\0"
  /* 5924 */ "dpax.w.ph\t\0"
  /* 5935 */ "dpsx.w.ph\t\0"
  /* 5946 */ "ush\t\0"
  /* 5951 */ "dmuh\t\0"
  /* 5957 */ "synci\t\0"
  /* 5964 */ "daddi\t\0"
  /* 5971 */ "andi\t\0"
  /* 5977 */ "tgei\t\0"
  /* 5983 */ "snei\t\0"
  /* 5989 */ "tnei\t\0"
  /* 5995 */ "dahi\t\0"
  /* 6001 */ "mfhi\t\0"
  /* 6007 */ "mthi\t\0"
  /* 6013 */ ".align 2\n\tli\t\0"
  /* 6027 */ "dli\t\0"
  /* 6032 */ "cmpi\t\0"
  /* 6038 */ "seqi\t\0"
  /* 6044 */ "teqi\t\0"
  /* 6050 */ "xori\t\0"
  /* 6056 */ "dati\t\0"
  /* 6062 */ "slti\t\0"
  /* 6068 */ "tlti\t\0"
  /* 6074 */ "daui\t\0"
  /* 6080 */ "lui\t\0"
  /* 6085 */ "ginvi\t\0"
  /* 6092 */ "j\t\0"
  /* 6095 */ "break\t\0"
  /* 6102 */ "fork\t\0"
  /* 6108 */ "cvt.d.l\t\0"
  /* 6117 */ "cvt.s.l\t\0"
  /* 6126 */ "bal\t\0"
  /* 6131 */ "jal\t\0"
  /* 6136 */ "bgezal\t\0"
  /* 6144 */ "bltzal\t\0"
  /* 6152 */ "dpau.h.qbl\t\0"
  /* 6164 */ "dpsu.h.qbl\t\0"
  /* 6176 */ "muleu_s.ph.qbl\t\0"
  /* 6192 */ "preceu.ph.qbl\t\0"
  /* 6207 */ "precequ.ph.qbl\t\0"
  /* 6223 */ "ldl\t\0"
  /* 6228 */ "sdl\t\0"
  /* 6233 */ "bgel\t\0"
  /* 6239 */ "blel\t\0"
  /* 6245 */ "bnel\t\0"
  /* 6251 */ "bc1fl\t\0"
  /* 6258 */ "maq_sa.w.phl\t\0"
  /* 6272 */ "preceq.w.phl\t\0"
  /* 6286 */ "maq_s.w.phl\t\0"
  /* 6299 */ "muleq_s.w.phl\t\0"
  /* 6314 */ "hypcall\t\0"
  /* 6323 */ "syscall\t\0"
  /* 6332 */ "bgezall\t\0"
  /* 6341 */ "bltzall\t\0"
  /* 6350 */ "dsll\t\0"
  /* 6356 */ "drol\t\0"
  /* 6362 */ "cvt.s.pl\t\0"
  /* 6372 */ "beql\t\0"
  /* 6378 */ "dsrl\t\0"
  /* 6384 */ "bc1tl\t\0"
  /* 6391 */ "bgtl\t\0"
  /* 6397 */ "bltl\t\0"
  /* 6403 */ "bgeul\t\0"
  /* 6410 */ "bleul\t\0"
  /* 6417 */ "dmul\t\0"
  /* 6423 */ "bgtul\t\0"
  /* 6430 */ "bltul\t\0"
  /* 6437 */ "lwl\t\0"
  /* 6442 */ "swl\t\0"
  /* 6447 */ "bgezl\t\0"
  /* 6454 */ "blezl\t\0"
  /* 6461 */ "bgtzl\t\0"
  /* 6468 */ "bltzl\t\0"
  /* 6475 */ "drem\t\0"
  /* 6481 */ "dinsm\t\0"
  /* 6488 */ "dextm\t\0"
  /* 6495 */ "lwm\t\0"
  /* 6500 */ "swm\t\0"
  /* 6505 */ "balign\t\0"
  /* 6513 */ "dalign\t\0"
  /* 6521 */ "movn\t\0"
  /* 6527 */ "dclo\t\0"
  /* 6533 */ "mflo\t\0"
  /* 6539 */ "shilo\t\0"
  /* 6546 */ "mtlo\t\0"
  /* 6552 */ "dmulo\t\0"
  /* 6559 */ "dbitswap\t\0"
  /* 6569 */ "sdbbp\t\0"
  /* 6576 */ "extpdp\t\0"
  /* 6584 */ "movep\t\0"
  /* 6591 */ "mthlip\t\0"
  /* 6599 */ "cmp\t\0"
  /* 6604 */ "dpop\t\0"
  /* 6610 */ "addiur1sp\t\0"
  /* 6621 */ "load_ccond_dsp\t\0"
  /* 6637 */ "store_ccond_dsp\t\0"
  /* 6654 */ "rddsp\t\0"
  /* 6661 */ "wrdsp\t\0"
  /* 6668 */ "jrcaddiusp\t\0"
  /* 6680 */ "jraddiusp\t\0"
  /* 6691 */ "swsp\t\0"
  /* 6697 */ "extp\t\0"
  /* 6703 */ "dvp\t\0"
  /* 6708 */ "evp\t\0"
  /* 6713 */ "lwp\t\0"
  /* 6718 */ "swp\t\0"
  /* 6723 */ "beq\t\0"
  /* 6728 */ "seq\t\0"
  /* 6733 */ "teq\t\0"
  /* 6738 */ "dpau.h.qbr\t\0"
  /* 6750 */ "dpsu.h.qbr\t\0"
  /* 6762 */ "muleu_s.ph.qbr\t\0"
  /* 6778 */ "preceu.ph.qbr\t\0"
  /* 6793 */ "precequ.ph.qbr\t\0"
  /* 6809 */ "ldr\t\0"
  /* 6814 */ "sdr\t\0"
  /* 6819 */ "maq_sa.w.phr\t\0"
  /* 6833 */ "preceq.w.phr\t\0"
  /* 6847 */ "maq_s.w.phr\t\0"
  /* 6860 */ "muleq_s.w.phr\t\0"
  /* 6875 */ "jr\t\0"
  /* 6879 */ "jalr\t\0"
  /* 6885 */ "nor\t\0"
  /* 6890 */ "dror\t\0"
  /* 6896 */ "xor\t\0"
  /* 6901 */ "rdpgpr\t\0"
  /* 6909 */ "wrpgpr\t\0"
  /* 6917 */ "mftr\t\0"
  /* 6923 */ "drotr\t\0"
  /* 6930 */ "mttr\t\0"
  /* 6936 */ "rdhwr\t\0"
  /* 6943 */ "lwr\t\0"
  /* 6948 */ "swr\t\0"
  /* 6953 */ "mina.s\t\0"
  /* 6961 */ "maxa.s\t\0"
  /* 6969 */ "nmsub.s\t\0"
  /* 6978 */ "cvt.d.s\t\0"
  /* 6987 */ "nmadd.s\t\0"
  /* 6996 */ "c.nge.s\t\0"
  /* 7005 */ "c.le.s\t\0"
  /* 7013 */ "cmp.le.s\t\0"
  /* 7023 */ "c.ngle.s\t\0"
  /* 7033 */ "c.ole.s\t\0"
  /* 7042 */ "cmp.sle.s\t\0"
  /* 7053 */ "c.ule.s\t\0"
  /* 7062 */ "cmp.ule.s\t\0"
  /* 7073 */ "cmp.sule.s\t\0"
  /* 7085 */ "c.f.s\t\0"
  /* 7092 */ "cmp.af.s\t\0"
  /* 7102 */ "cmp.saf.s\t\0"
  /* 7113 */ "msubf.s\t\0"
  /* 7122 */ "maddf.s\t\0"
  /* 7131 */ "c.sf.s\t\0"
  /* 7139 */ "movf.s\t\0"
  /* 7147 */ "neg.s\t\0"
  /* 7154 */ "li.s\t\0"
  /* 7160 */ "trunc.l.s\t\0"
  /* 7171 */ "round.l.s\t\0"
  /* 7182 */ "ceil.l.s\t\0"
  /* 7192 */ "floor.l.s\t\0"
  /* 7203 */ "cvt.l.s\t\0"
  /* 7212 */ "sel.s\t\0"
  /* 7219 */ "c.ngl.s\t\0"
  /* 7228 */ "mul.s\t\0"
  /* 7235 */ "min.s\t\0"
  /* 7242 */ "c.un.s\t\0"
  /* 7250 */ "cmp.un.s\t\0"
  /* 7260 */ "cmp.sun.s\t\0"
  /* 7271 */ "movn.s\t\0"
  /* 7279 */ "recip.s\t\0"
  /* 7288 */ "c.eq.s\t\0"
  /* 7296 */ "cmp.eq.s\t\0"
  /* 7306 */ "c.seq.s\t\0"
  /* 7315 */ "cmp.seq.s\t\0"
  /* 7326 */ "c.ueq.s\t\0"
  /* 7335 */ "cmp.ueq.s\t\0"
  /* 7346 */ "cmp.sueq.s\t\0"
  /* 7358 */ "abs.s\t\0"
  /* 7365 */ "cvt.ps.s\t\0"
  /* 7375 */ "class.s\t\0"
  /* 7384 */ "c.ngt.s\t\0"
  /* 7393 */ "c.lt.s\t\0"
  /* 7401 */ "cmp.lt.s\t\0"
  /* 7411 */ "c.olt.s\t\0"
  /* 7420 */ "cmp.slt.s\t\0"
  /* 7431 */ "c.ult.s\t\0"
  /* 7440 */ "cmp.ult.s\t\0"
  /* 7451 */ "cmp.sult.s\t\0"
  /* 7463 */ "rint.s\t\0"
  /* 7471 */ "rsqrt.s\t\0"
  /* 7480 */ "movt.s\t\0"
  /* 7488 */ "div.s\t\0"
  /* 7495 */ "mov.s\t\0"
  /* 7502 */ "trunc.w.s\t\0"
  /* 7513 */ "round.w.s\t\0"
  /* 7524 */ "ceil.w.s\t\0"
  /* 7534 */ "floor.w.s\t\0"
  /* 7545 */ "cvt.w.s\t\0"
  /* 7554 */ "max.s\t\0"
  /* 7561 */ "selnez.s\t\0"
  /* 7571 */ "seleqz.s\t\0"
  /* 7581 */ "movz.s\t\0"
  /* 7589 */ "abs\t\0"
  /* 7594 */ "jals\t\0"
  /* 7600 */ "bgezals\t\0"
  /* 7609 */ "bltzals\t\0"
  /* 7618 */ "cins\t\0"
  /* 7624 */ "dins\t\0"
  /* 7630 */ "sub.ps\t\0"
  /* 7638 */ "add.ps\t\0"
  /* 7646 */ "pll.ps\t\0"
  /* 7654 */ "mul.ps\t\0"
  /* 7662 */ "pul.ps\t\0"
  /* 7670 */ "addr.ps\t\0"
  /* 7679 */ "mulr.ps\t\0"
  /* 7688 */ "plu.ps\t\0"
  /* 7696 */ "puu.ps\t\0"
  /* 7704 */ "cvt.pw.ps\t\0"
  /* 7715 */ "jalrs\t\0"
  /* 7722 */ "exts\t\0"
  /* 7728 */ "lwxs\t\0"
  /* 7734 */ "bc1t\t\0"
  /* 7740 */ "bgt\t\0"
  /* 7745 */ "sgt\t\0"
  /* 7750 */ "wait\t\0"
  /* 7756 */ "blt\t\0"
  /* 7761 */ "slt\t\0"
  /* 7766 */ "tlt\t\0"
  /* 7771 */ "dmult\t\0"
  /* 7778 */ "dmt\t\0"
  /* 7783 */ "emt\t\0"
  /* 7788 */ "not\t\0"
  /* 7793 */ "ginvt\t\0"
  /* 7800 */ "movt\t\0"
  /* 7806 */ "dext\t\0"
  /* 7812 */ "lbu\t\0"
  /* 7817 */ "dsubu\t\0"
  /* 7824 */ "msubu\t\0"
  /* 7831 */ "baddu\t\0"
  /* 7838 */ "daddu\t\0"
  /* 7845 */ "maddu\t\0"
  /* 7852 */ "dmodu\t\0"
  /* 7859 */ "bgeu\t\0"
  /* 7865 */ "sgeu\t\0"
  /* 7871 */ "tgeu\t\0"
  /* 7877 */ "bleu\t\0"
  /* 7883 */ "sleu\t\0"
  /* 7889 */ "ulhu\t\0"
  /* 7895 */ "dmuhu\t\0"
  /* 7902 */ "daddiu\t\0"
  /* 7910 */ "tgeiu\t\0"
  /* 7917 */ "sltiu\t\0"
  /* 7924 */ "tltiu\t\0"
  /* 7931 */ "v3mulu\t\0"
  /* 7939 */ "dmulu\t\0"
  /* 7946 */ "vmulu\t\0"
  /* 7953 */ "dremu\t\0"
  /* 7960 */ "dmulou\t\0"
  /* 7968 */ "cvt.s.pu\t\0"
  /* 7978 */ "dinsu\t\0"
  /* 7985 */ "bgtu\t\0"
  /* 7991 */ "sgtu\t\0"
  /* 7997 */ "bltu\t\0"
  /* 8003 */ "sltu\t\0"
  /* 8009 */ "tltu\t\0"
  /* 8015 */ "dmultu\t\0"
  /* 8023 */ "dextu\t\0"
  /* 8030 */ "ddivu\t\0"
  /* 8037 */ "lwu\t\0"
  /* 8042 */ "and.v\t\0"
  /* 8049 */ "move.v\t\0"
  /* 8057 */ "bsel.v\t\0"
  /* 8065 */ "nor.v\t\0"
  /* 8072 */ "xor.v\t\0"
  /* 8079 */ "bz.v\t\0"
  /* 8085 */ "bmz.v\t\0"
  /* 8092 */ "bnz.v\t\0"
  /* 8099 */ "bmnz.v\t\0"
  /* 8107 */ "dsrav\t\0"
  /* 8114 */ "bitrev\t\0"
  /* 8122 */ "ddiv\t\0"
  /* 8128 */ "dsllv\t\0"
  /* 8135 */ "dsrlv\t\0"
  /* 8142 */ "shilov\t\0"
  /* 8150 */ "extpdpv\t\0"
  /* 8159 */ "extpv\t\0"
  /* 8166 */ "drotrv\t\0"
  /* 8174 */ "insv\t\0"
  /* 8180 */ "flog2.w\t\0"
  /* 8189 */ "fexp2.w\t\0"
  /* 8198 */ "add_a.w\t\0"
  /* 8207 */ "fmin_a.w\t\0"
  /* 8217 */ "adds_a.w\t\0"
  /* 8227 */ "fmax_a.w\t\0"
  /* 8237 */ "sra.w\t\0"
  /* 8244 */ "fsub.w\t\0"
  /* 8252 */ "fmsub.w\t\0"
  /* 8261 */ "nloc.w\t\0"
  /* 8269 */ "nlzc.w\t\0"
  /* 8277 */ "cvt.d.w\t\0"
  /* 8286 */ "fadd.w\t\0"
  /* 8294 */ "fmadd.w\t\0"
  /* 8303 */ "sld.w\t\0"
  /* 8310 */ "pckod.w\t\0"
  /* 8319 */ "ilvod.w\t\0"
  /* 8328 */ "fcle.w\t\0"
  /* 8336 */ "fsle.w\t\0"
  /* 8344 */ "fcule.w\t\0"
  /* 8353 */ "fsule.w\t\0"
  /* 8362 */ "fcne.w\t\0"
  /* 8370 */ "fsne.w\t\0"
  /* 8378 */ "fcune.w\t\0"
  /* 8387 */ "fsune.w\t\0"
  /* 8396 */ "insve.w\t\0"
  /* 8405 */ "fcaf.w\t\0"
  /* 8413 */ "fsaf.w\t\0"
  /* 8421 */ "vshf.w\t\0"
  /* 8429 */ "bneg.w\t\0"
  /* 8437 */ "precr_sra.ph.w\t\0"
  /* 8453 */ "precrq.ph.w\t\0"
  /* 8466 */ "precr_sra_r.ph.w\t\0"
  /* 8484 */ "precrq_rs.ph.w\t\0"
  /* 8500 */ "subqh.w\t\0"
  /* 8509 */ "addqh.w\t\0"
  /* 8518 */ "srai.w\t\0"
  /* 8526 */ "sldi.w\t\0"
  /* 8534 */ "bnegi.w\t\0"
  /* 8543 */ "slli.w\t\0"
  /* 8551 */ "srli.w\t\0"
  /* 8559 */ "binsli.w\t\0"
  /* 8569 */ "ceqi.w\t\0"
  /* 8577 */ "srari.w\t\0"
  /* 8586 */ "bclri.w\t\0"
  /* 8595 */ "srlri.w\t\0"
  /* 8604 */ "binsri.w\t\0"
  /* 8614 */ "splati.w\t\0"
  /* 8624 */ "bseti.w\t\0"
  /* 8633 */ "subvi.w\t\0"
  /* 8642 */ "addvi.w\t\0"
  /* 8651 */ "dpaq_sa.l.w\t\0"
  /* 8664 */ "dpsq_sa.l.w\t\0"
  /* 8677 */ "fill.w\t\0"
  /* 8685 */ "sll.w\t\0"
  /* 8692 */ "fexupl.w\t\0"
  /* 8702 */ "ffql.w\t\0"
  /* 8710 */ "srl.w\t\0"
  /* 8717 */ "binsl.w\t\0"
  /* 8726 */ "fmul.w\t\0"
  /* 8734 */ "ilvl.w\t\0"
  /* 8742 */ "fmin.w\t\0"
  /* 8750 */ "fcun.w\t\0"
  /* 8758 */ "fsun.w\t\0"
  /* 8766 */ "fexdo.w\t\0"
  /* 8775 */ "frcp.w\t\0"
  /* 8783 */ "msub_q.w\t\0"
  /* 8793 */ "madd_q.w\t\0"
  /* 8803 */ "mul_q.w\t\0"
  /* 8812 */ "msubr_q.w\t\0"
  /* 8823 */ "maddr_q.w\t\0"
  /* 8834 */ "mulr_q.w\t\0"
  /* 8844 */ "fceq.w\t\0"
  /* 8852 */ "fseq.w\t\0"
  /* 8860 */ "fcueq.w\t\0"
  /* 8869 */ "fsueq.w\t\0"
  /* 8878 */ "ftq.w\t\0"
  /* 8885 */ "shra_r.w\t\0"
  /* 8895 */ "subqh_r.w\t\0"
  /* 8906 */ "addqh_r.w\t\0"
  /* 8917 */ "extr_r.w\t\0"
  /* 8927 */ "shrav_r.w\t\0"
  /* 8938 */ "extrv_r.w\t\0"
  /* 8949 */ "srar.w\t\0"
  /* 8957 */ "bclr.w\t\0"
  /* 8965 */ "srlr.w\t\0"
  /* 8973 */ "fcor.w\t\0"
  /* 8981 */ "fsor.w\t\0"
  /* 8989 */ "fexupr.w\t\0"
  /* 8999 */ "ffqr.w\t\0"
  /* 9007 */ "binsr.w\t\0"
  /* 9016 */ "extr.w\t\0"
  /* 9024 */ "ilvr.w\t\0"
  /* 9032 */ "cvt.s.w\t\0"
  /* 9041 */ "asub_s.w\t\0"
  /* 9051 */ "hsub_s.w\t\0"
  /* 9061 */ "dpsub_s.w\t\0"
  /* 9072 */ "ftrunc_s.w\t\0"
  /* 9084 */ "hadd_s.w\t\0"
  /* 9094 */ "dpadd_s.w\t\0"
  /* 9105 */ "mod_s.w\t\0"
  /* 9114 */ "cle_s.w\t\0"
  /* 9123 */ "ave_s.w\t\0"
  /* 9132 */ "clei_s.w\t\0"
  /* 9142 */ "mini_s.w\t\0"
  /* 9152 */ "clti_s.w\t\0"
  /* 9162 */ "maxi_s.w\t\0"
  /* 9172 */ "shll_s.w\t\0"
  /* 9182 */ "min_s.w\t\0"
  /* 9191 */ "dotp_s.w\t\0"
  /* 9201 */ "subq_s.w\t\0"
  /* 9211 */ "addq_s.w\t\0"
  /* 9221 */ "mulq_s.w\t\0"
  /* 9231 */ "absq_s.w\t\0"
  /* 9241 */ "aver_s.w\t\0"
  /* 9251 */ "subs_s.w\t\0"
  /* 9261 */ "adds_s.w\t\0"
  /* 9271 */ "sat_s.w\t\0"
  /* 9280 */ "clt_s.w\t\0"
  /* 9289 */ "ffint_s.w\t\0"
  /* 9300 */ "ftint_s.w\t\0"
  /* 9311 */ "subsuu_s.w\t\0"
  /* 9323 */ "div_s.w\t\0"
  /* 9332 */ "shllv_s.w\t\0"
  /* 9343 */ "max_s.w\t\0"
  /* 9352 */ "copy_s.w\t\0"
  /* 9362 */ "mulq_rs.w\t\0"
  /* 9373 */ "extr_rs.w\t\0"
  /* 9384 */ "extrv_rs.w\t\0"
  /* 9396 */ "fclass.w\t\0"
  /* 9406 */ "splat.w\t\0"
  /* 9415 */ "bset.w\t\0"
  /* 9423 */ "fclt.w\t\0"
  /* 9431 */ "fslt.w\t\0"
  /* 9439 */ "fcult.w\t\0"
  /* 9448 */ "fsult.w\t\0"
  /* 9457 */ "pcnt.w\t\0"
  /* 9465 */ "frint.w\t\0"
  /* 9474 */ "insert.w\t\0"
  /* 9484 */ "fsqrt.w\t\0"
  /* 9493 */ "frsqrt.w\t\0"
  /* 9503 */ "st.w\t\0"
  /* 9509 */ "asub_u.w\t\0"
  /* 9519 */ "hsub_u.w\t\0"
  /* 9529 */ "dpsub_u.w\t\0"
  /* 9540 */ "ftrunc_u.w\t\0"
  /* 9552 */ "hadd_u.w\t\0"
  /* 9562 */ "dpadd_u.w\t\0"
  /* 9573 */ "mod_u.w\t\0"
  /* 9582 */ "cle_u.w\t\0"
  /* 9591 */ "ave_u.w\t\0"
  /* 9600 */ "clei_u.w\t\0"
  /* 9610 */ "mini_u.w\t\0"
  /* 9620 */ "clti_u.w\t\0"
  /* 9630 */ "maxi_u.w\t\0"
  /* 9640 */ "min_u.w\t\0"
  /* 9649 */ "dotp_u.w\t\0"
  /* 9659 */ "aver_u.w\t\0"
  /* 9669 */ "subs_u.w\t\0"
  /* 9679 */ "adds_u.w\t\0"
  /* 9689 */ "subsus_u.w\t\0"
  /* 9701 */ "sat_u.w\t\0"
  /* 9710 */ "clt_u.w\t\0"
  /* 9719 */ "ffint_u.w\t\0"
  /* 9730 */ "ftint_u.w\t\0"
  /* 9741 */ "div_u.w\t\0"
  /* 9750 */ "max_u.w\t\0"
  /* 9759 */ "copy_u.w\t\0"
  /* 9769 */ "msubv.w\t\0"
  /* 9778 */ "maddv.w\t\0"
  /* 9787 */ "pckev.w\t\0"
  /* 9796 */ "ilvev.w\t\0"
  /* 9805 */ "fdiv.w\t\0"
  /* 9813 */ "mulv.w\t\0"
  /* 9821 */ "extrv.w\t\0"
  /* 9830 */ "fmax.w\t\0"
  /* 9838 */ "bz.w\t\0"
  /* 9844 */ "bnz.w\t\0"
  /* 9851 */ "crc32w\t\0"
  /* 9859 */ "crc32cw\t\0"
  /* 9868 */ "ulw\t\0"
  /* 9873 */ "cvt.ps.pw\t\0"
  /* 9884 */ "usw\t\0"
  /* 9889 */ "prefx\t\0"
  /* 9896 */ "lhx\t\0"
  /* 9901 */ "jalx\t\0"
  /* 9907 */ "lbux\t\0"
  /* 9913 */ "lwx\t\0"
  /* 9918 */ "bgez\t\0"
  /* 9924 */ "blez\t\0"
  /* 9930 */ "bnez\t\0"
  /* 9936 */ "selnez\t\0"
  /* 9944 */ "btnez\t\0"
  /* 9951 */ "dclz\t\0"
  /* 9957 */ "beqz\t\0"
  /* 9963 */ "seleqz\t\0"
  /* 9971 */ "bteqz\t\0"
  /* 9978 */ "bgtz\t\0"
  /* 9984 */ "bltz\t\0"
  /* 9990 */ "movz\t\0"
  /* 9996 */ "seb\t \0"
  /* 10002 */ "seh\t \0"
  /* 10008 */ "ddivu\t$zero, \0"
  /* 10022 */ "ddiv\t$zero, \0"
  /* 10035 */ "addiu\t$sp, \0"
  /* 10047 */ "mftc0 \0"
  /* 10054 */ "mttc0 \0"
  /* 10061 */ "mfthc1 \0"
  /* 10069 */ "mtthc1 \0"
  /* 10077 */ "cftc1 \0"
  /* 10084 */ "mftc1 \0"
  /* 10091 */ "cttc1 \0"
  /* 10098 */ "mttc1 \0"
  /* 10105 */ "sync \0"
  /* 10111 */ "ld \0"
  /* 10115 */ "\t.word \0"
  /* 10123 */ "sd \0"
  /* 10127 */ "sne \0"
  /* 10132 */ "mfthi \0"
  /* 10139 */ "mtthi \0"
  /* 10146 */ "mftlo \0"
  /* 10153 */ "mttlo \0"
  /* 10160 */ "mftdsp \0"
  /* 10168 */ "mttdsp \0"
  /* 10176 */ "seq \0"
  /* 10181 */ "mftgpr \0"
  /* 10189 */ "mttgpr \0"
  /* 10197 */ "dext \0"
  /* 10203 */ "mftacx \0"
  /* 10211 */ "mttacx \0"
  /* 10219 */ "bc1nez \0"
  /* 10227 */ "bc2nez \0"
  /* 10235 */ "bc1eqz \0"
  /* 10243 */ "bc2eqz \0"
  /* 10251 */ "# XRay Function Patchable RET.\0"
  /* 10282 */ "c.\0"
  /* 10285 */ "# XRay Typed Event Log.\0"
  /* 10309 */ "# XRay Custom Event Log.\0"
  /* 10334 */ "# XRay Function Enter.\0"
  /* 10357 */ "# XRay Tail Call Exit.\0"
  /* 10380 */ "# XRay Function Exit.\0"
  /* 10402 */ "break 0\0"
  /* 10410 */ "LIFETIME_END\0"
  /* 10423 */ "PSEUDO_PROBE\0"
  /* 10436 */ "BUNDLE\0"
  /* 10443 */ "DBG_VALUE\0"
  /* 10453 */ "DBG_INSTR_REF\0"
  /* 10467 */ "DBG_PHI\0"
  /* 10475 */ "DBG_LABEL\0"
  /* 10485 */ "LIFETIME_START\0"
  /* 10500 */ "DBG_VALUE_LIST\0"
  /* 10515 */ "jrc\t$ra\0"
  /* 10523 */ "jr\t$ra\0"
  /* 10530 */ "ehb\0"
  /* 10534 */ "eretnc\0"
  /* 10541 */ "pause\0"
  /* 10547 */ "tlbinvf\0"
  /* 10555 */ "tlbginvf\0"
  /* 10564 */ "tlbwi\0"
  /* 10570 */ "tlbgwi\0"
  /* 10577 */ "# FEntry call\0"
  /* 10591 */ "foo\0"
  /* 10595 */ "tlbp\0"
  /* 10600 */ "tlbgp\0"
  /* 10606 */ "ssnop\0"
  /* 10612 */ "tlbr\0"
  /* 10617 */ "tlbgr\0"
  /* 10623 */ "tlbwr\0"
  /* 10629 */ "tlbgwr\0"
  /* 10636 */ "deret\0"
  /* 10642 */ "wait\0"
  /* 10647 */ "tlbinv\0"
  /* 10654 */ "tlbginv\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

  static const uint32_t OpInfo0[] = {
    0U,	// PHI
    0U,	// INLINEASM
    0U,	// INLINEASM_BR
    0U,	// CFI_INSTRUCTION
    0U,	// EH_LABEL
    0U,	// GC_LABEL
    0U,	// ANNOTATION_LABEL
    0U,	// KILL
    0U,	// EXTRACT_SUBREG
    0U,	// INSERT_SUBREG
    0U,	// IMPLICIT_DEF
    0U,	// SUBREG_TO_REG
    0U,	// COPY_TO_REGCLASS
    10444U,	// DBG_VALUE
    10501U,	// DBG_VALUE_LIST
    10454U,	// DBG_INSTR_REF
    10468U,	// DBG_PHI
    10476U,	// DBG_LABEL
    0U,	// REG_SEQUENCE
    0U,	// COPY
    10437U,	// BUNDLE
    10486U,	// LIFETIME_START
    10411U,	// LIFETIME_END
    10424U,	// PSEUDO_PROBE
    0U,	// ARITH_FENCE
    0U,	// STACKMAP
    10578U,	// FENTRY_CALL
    0U,	// PATCHPOINT
    0U,	// LOAD_STACK_GUARD
    0U,	// PREALLOCATED_SETUP
    0U,	// PREALLOCATED_ARG
    0U,	// STATEPOINT
    0U,	// LOCAL_ESCAPE
    0U,	// FAULTING_OP
    0U,	// PATCHABLE_OP
    10335U,	// PATCHABLE_FUNCTION_ENTER
    10252U,	// PATCHABLE_RET
    10381U,	// PATCHABLE_FUNCTION_EXIT
    10358U,	// PATCHABLE_TAIL_CALL
    10310U,	// PATCHABLE_EVENT_CALL
    10286U,	// PATCHABLE_TYPED_EVENT_CALL
    0U,	// ICALL_BRANCH_FUNNEL
    0U,	// MEMBARRIER
    0U,	// G_ASSERT_SEXT
    0U,	// G_ASSERT_ZEXT
    0U,	// G_ASSERT_ALIGN
    0U,	// G_ADD
    0U,	// G_SUB
    0U,	// G_MUL
    0U,	// G_SDIV
    0U,	// G_UDIV
    0U,	// G_SREM
    0U,	// G_UREM
    0U,	// G_SDIVREM
    0U,	// G_UDIVREM
    0U,	// G_AND
    0U,	// G_OR
    0U,	// G_XOR
    0U,	// G_IMPLICIT_DEF
    0U,	// G_PHI
    0U,	// G_FRAME_INDEX
    0U,	// G_GLOBAL_VALUE
    0U,	// G_EXTRACT
    0U,	// G_UNMERGE_VALUES
    0U,	// G_INSERT
    0U,	// G_MERGE_VALUES
    0U,	// G_BUILD_VECTOR
    0U,	// G_BUILD_VECTOR_TRUNC
    0U,	// G_CONCAT_VECTORS
    0U,	// G_PTRTOINT
    0U,	// G_INTTOPTR
    0U,	// G_BITCAST
    0U,	// G_FREEZE
    0U,	// G_INTRINSIC_FPTRUNC_ROUND
    0U,	// G_INTRINSIC_TRUNC
    0U,	// G_INTRINSIC_ROUND
    0U,	// G_INTRINSIC_LRINT
    0U,	// G_INTRINSIC_ROUNDEVEN
    0U,	// G_READCYCLECOUNTER
    0U,	// G_LOAD
    0U,	// G_SEXTLOAD
    0U,	// G_ZEXTLOAD
    0U,	// G_INDEXED_LOAD
    0U,	// G_INDEXED_SEXTLOAD
    0U,	// G_INDEXED_ZEXTLOAD
    0U,	// G_STORE
    0U,	// G_INDEXED_STORE
    0U,	// G_ATOMIC_CMPXCHG_WITH_SUCCESS
    0U,	// G_ATOMIC_CMPXCHG
    0U,	// G_ATOMICRMW_XCHG
    0U,	// G_ATOMICRMW_ADD
    0U,	// G_ATOMICRMW_SUB
    0U,	// G_ATOMICRMW_AND
    0U,	// G_ATOMICRMW_NAND
    0U,	// G_ATOMICRMW_OR
    0U,	// G_ATOMICRMW_XOR
    0U,	// G_ATOMICRMW_MAX
    0U,	// G_ATOMICRMW_MIN
    0U,	// G_ATOMICRMW_UMAX
    0U,	// G_ATOMICRMW_UMIN
    0U,	// G_ATOMICRMW_FADD
    0U,	// G_ATOMICRMW_FSUB
    0U,	// G_ATOMICRMW_FMAX
    0U,	// G_ATOMICRMW_FMIN
    0U,	// G_ATOMICRMW_UINC_WRAP
    0U,	// G_ATOMICRMW_UDEC_WRAP
    0U,	// G_FENCE
    0U,	// G_BRCOND
    0U,	// G_BRINDIRECT
    0U,	// G_INVOKE_REGION_START
    0U,	// G_INTRINSIC
    0U,	// G_INTRINSIC_W_SIDE_EFFECTS
    0U,	// G_ANYEXT
    0U,	// G_TRUNC
    0U,	// G_CONSTANT
    0U,	// G_FCONSTANT
    0U,	// G_VASTART
    0U,	// G_VAARG
    0U,	// G_SEXT
    0U,	// G_SEXT_INREG
    0U,	// G_ZEXT
    0U,	// G_SHL
    0U,	// G_LSHR
    0U,	// G_ASHR
    0U,	// G_FSHL
    0U,	// G_FSHR
    0U,	// G_ROTR
    0U,	// G_ROTL
    0U,	// G_ICMP
    0U,	// G_FCMP
    0U,	// G_SELECT
    0U,	// G_UADDO
    0U,	// G_UADDE
    0U,	// G_USUBO
    0U,	// G_USUBE
    0U,	// G_SADDO
    0U,	// G_SADDE
    0U,	// G_SSUBO
    0U,	// G_SSUBE
    0U,	// G_UMULO
    0U,	// G_SMULO
    0U,	// G_UMULH
    0U,	// G_SMULH
    0U,	// G_UADDSAT
    0U,	// G_SADDSAT
    0U,	// G_USUBSAT
    0U,	// G_SSUBSAT
    0U,	// G_USHLSAT
    0U,	// G_SSHLSAT
    0U,	// G_SMULFIX
    0U,	// G_UMULFIX
    0U,	// G_SMULFIXSAT
    0U,	// G_UMULFIXSAT
    0U,	// G_SDIVFIX
    0U,	// G_UDIVFIX
    0U,	// G_SDIVFIXSAT
    0U,	// G_UDIVFIXSAT
    0U,	// G_FADD
    0U,	// G_FSUB
    0U,	// G_FMUL
    0U,	// G_FMA
    0U,	// G_FMAD
    0U,	// G_FDIV
    0U,	// G_FREM
    0U,	// G_FPOW
    0U,	// G_FPOWI
    0U,	// G_FEXP
    0U,	// G_FEXP2
    0U,	// G_FLOG
    0U,	// G_FLOG2
    0U,	// G_FLOG10
    0U,	// G_FNEG
    0U,	// G_FPEXT
    0U,	// G_FPTRUNC
    0U,	// G_FPTOSI
    0U,	// G_FPTOUI
    0U,	// G_SITOFP
    0U,	// G_UITOFP
    0U,	// G_FABS
    0U,	// G_FCOPYSIGN
    0U,	// G_IS_FPCLASS
    0U,	// G_FCANONICALIZE
    0U,	// G_FMINNUM
    0U,	// G_FMAXNUM
    0U,	// G_FMINNUM_IEEE
    0U,	// G_FMAXNUM_IEEE
    0U,	// G_FMINIMUM
    0U,	// G_FMAXIMUM
    0U,	// G_PTR_ADD
    0U,	// G_PTRMASK
    0U,	// G_SMIN
    0U,	// G_SMAX
    0U,	// G_UMIN
    0U,	// G_UMAX
    0U,	// G_ABS
    0U,	// G_LROUND
    0U,	// G_LLROUND
    0U,	// G_BR
    0U,	// G_BRJT
    0U,	// G_INSERT_VECTOR_ELT
    0U,	// G_EXTRACT_VECTOR_ELT
    0U,	// G_SHUFFLE_VECTOR
    0U,	// G_CTTZ
    0U,	// G_CTTZ_ZERO_UNDEF
    0U,	// G_CTLZ
    0U,	// G_CTLZ_ZERO_UNDEF
    0U,	// G_CTPOP
    0U,	// G_BSWAP
    0U,	// G_BITREVERSE
    0U,	// G_FCEIL
    0U,	// G_FCOS
    0U,	// G_FSIN
    0U,	// G_FSQRT
    0U,	// G_FFLOOR
    0U,	// G_FRINT
    0U,	// G_FNEARBYINT
    0U,	// G_ADDRSPACE_CAST
    0U,	// G_BLOCK_ADDR
    0U,	// G_JUMP_TABLE
    0U,	// G_DYN_STACKALLOC
    0U,	// G_STRICT_FADD
    0U,	// G_STRICT_FSUB
    0U,	// G_STRICT_FMUL
    0U,	// G_STRICT_FDIV
    0U,	// G_STRICT_FREM
    0U,	// G_STRICT_FMA
    0U,	// G_STRICT_FSQRT
    0U,	// G_READ_REGISTER
    0U,	// G_WRITE_REGISTER
    0U,	// G_MEMCPY
    0U,	// G_MEMCPY_INLINE
    0U,	// G_MEMMOVE
    0U,	// G_MEMSET
    0U,	// G_BZERO
    0U,	// G_VECREDUCE_SEQ_FADD
    0U,	// G_VECREDUCE_SEQ_FMUL
    0U,	// G_VECREDUCE_FADD
    0U,	// G_VECREDUCE_FMUL
    0U,	// G_VECREDUCE_FMAX
    0U,	// G_VECREDUCE_FMIN
    0U,	// G_VECREDUCE_ADD
    0U,	// G_VECREDUCE_MUL
    0U,	// G_VECREDUCE_AND
    0U,	// G_VECREDUCE_OR
    0U,	// G_VECREDUCE_XOR
    0U,	// G_VECREDUCE_SMAX
    0U,	// G_VECREDUCE_SMIN
    0U,	// G_VECREDUCE_UMAX
    0U,	// G_VECREDUCE_UMIN
    0U,	// G_SBFX
    0U,	// G_UBFX
    23974U,	// ABSMacro
    0U,	// ADJCALLSTACKDOWN
    0U,	// ADJCALLSTACKUP
    0U,	// AND_V_D_PSEUDO
    0U,	// AND_V_H_PSEUDO
    0U,	// AND_V_W_PSEUDO
    0U,	// ATOMIC_CMP_SWAP_I16
    0U,	// ATOMIC_CMP_SWAP_I16_POSTRA
    0U,	// ATOMIC_CMP_SWAP_I32
    0U,	// ATOMIC_CMP_SWAP_I32_POSTRA
    0U,	// ATOMIC_CMP_SWAP_I64
    0U,	// ATOMIC_CMP_SWAP_I64_POSTRA
    0U,	// ATOMIC_CMP_SWAP_I8
    0U,	// ATOMIC_CMP_SWAP_I8_POSTRA
    0U,	// ATOMIC_LOAD_ADD_I16
    0U,	// ATOMIC_LOAD_ADD_I16_POSTRA
    0U,	// ATOMIC_LOAD_ADD_I32
    0U,	// ATOMIC_LOAD_ADD_I32_POSTRA
    0U,	// ATOMIC_LOAD_ADD_I64
    0U,	// ATOMIC_LOAD_ADD_I64_POSTRA
    0U,	// ATOMIC_LOAD_ADD_I8
    0U,	// ATOMIC_LOAD_ADD_I8_POSTRA
    0U,	// ATOMIC_LOAD_AND_I16
    0U,	// ATOMIC_LOAD_AND_I16_POSTRA
    0U,	// ATOMIC_LOAD_AND_I32
    0U,	// ATOMIC_LOAD_AND_I32_POSTRA
    0U,	// ATOMIC_LOAD_AND_I64
    0U,	// ATOMIC_LOAD_AND_I64_POSTRA
    0U,	// ATOMIC_LOAD_AND_I8
    0U,	// ATOMIC_LOAD_AND_I8_POSTRA
    0U,	// ATOMIC_LOAD_MAX_I16
    0U,	// ATOMIC_LOAD_MAX_I16_POSTRA
    0U,	// ATOMIC_LOAD_MAX_I32
    0U,	// ATOMIC_LOAD_MAX_I32_POSTRA
    0U,	// ATOMIC_LOAD_MAX_I64
    0U,	// ATOMIC_LOAD_MAX_I64_POSTRA
    0U,	// ATOMIC_LOAD_MAX_I8
    0U,	// ATOMIC_LOAD_MAX_I8_POSTRA
    0U,	// ATOMIC_LOAD_MIN_I16
    0U,	// ATOMIC_LOAD_MIN_I16_POSTRA
    0U,	// ATOMIC_LOAD_MIN_I32
    0U,	// ATOMIC_LOAD_MIN_I32_POSTRA
    0U,	// ATOMIC_LOAD_MIN_I64
    0U,	// ATOMIC_LOAD_MIN_I64_POSTRA
    0U,	// ATOMIC_LOAD_MIN_I8
    0U,	// ATOMIC_LOAD_MIN_I8_POSTRA
    0U,	// ATOMIC_LOAD_NAND_I16
    0U,	// ATOMIC_LOAD_NAND_I16_POSTRA
    0U,	// ATOMIC_LOAD_NAND_I32
    0U,	// ATOMIC_LOAD_NAND_I32_POSTRA
    0U,	// ATOMIC_LOAD_NAND_I64
    0U,	// ATOMIC_LOAD_NAND_I64_POSTRA
    0U,	// ATOMIC_LOAD_NAND_I8
    0U,	// ATOMIC_LOAD_NAND_I8_POSTRA
    0U,	// ATOMIC_LOAD_OR_I16
    0U,	// ATOMIC_LOAD_OR_I16_POSTRA
    0U,	// ATOMIC_LOAD_OR_I32
    0U,	// ATOMIC_LOAD_OR_I32_POSTRA
    0U,	// ATOMIC_LOAD_OR_I64
    0U,	// ATOMIC_LOAD_OR_I64_POSTRA
    0U,	// ATOMIC_LOAD_OR_I8
    0U,	// ATOMIC_LOAD_OR_I8_POSTRA
    0U,	// ATOMIC_LOAD_SUB_I16
    0U,	// ATOMIC_LOAD_SUB_I16_POSTRA
    0U,	// ATOMIC_LOAD_SUB_I32
    0U,	// ATOMIC_LOAD_SUB_I32_POSTRA
    0U,	// ATOMIC_LOAD_SUB_I64
    0U,	// ATOMIC_LOAD_SUB_I64_POSTRA
    0U,	// ATOMIC_LOAD_SUB_I8
    0U,	// ATOMIC_LOAD_SUB_I8_POSTRA
    0U,	// ATOMIC_LOAD_UMAX_I16
    0U,	// ATOMIC_LOAD_UMAX_I16_POSTRA
    0U,	// ATOMIC_LOAD_UMAX_I32
    0U,	// ATOMIC_LOAD_UMAX_I32_POSTRA
    0U,	// ATOMIC_LOAD_UMAX_I64
    0U,	// ATOMIC_LOAD_UMAX_I64_POSTRA
    0U,	// ATOMIC_LOAD_UMAX_I8
    0U,	// ATOMIC_LOAD_UMAX_I8_POSTRA
    0U,	// ATOMIC_LOAD_UMIN_I16
    0U,	// ATOMIC_LOAD_UMIN_I16_POSTRA
    0U,	// ATOMIC_LOAD_UMIN_I32
    0U,	// ATOMIC_LOAD_UMIN_I32_POSTRA
    0U,	// ATOMIC_LOAD_UMIN_I64
    0U,	// ATOMIC_LOAD_UMIN_I64_POSTRA
    0U,	// ATOMIC_LOAD_UMIN_I8
    0U,	// ATOMIC_LOAD_UMIN_I8_POSTRA
    0U,	// ATOMIC_LOAD_XOR_I16
    0U,	// ATOMIC_LOAD_XOR_I16_POSTRA
    0U,	// ATOMIC_LOAD_XOR_I32
    0U,	// ATOMIC_LOAD_XOR_I32_POSTRA
    0U,	// ATOMIC_LOAD_XOR_I64
    0U,	// ATOMIC_LOAD_XOR_I64_POSTRA
    0U,	// ATOMIC_LOAD_XOR_I8
    0U,	// ATOMIC_LOAD_XOR_I8_POSTRA
    0U,	// ATOMIC_SWAP_I16
    0U,	// ATOMIC_SWAP_I16_POSTRA
    0U,	// ATOMIC_SWAP_I32
    0U,	// ATOMIC_SWAP_I32_POSTRA
    0U,	// ATOMIC_SWAP_I64
    0U,	// ATOMIC_SWAP_I64_POSTRA
    0U,	// ATOMIC_SWAP_I8
    0U,	// ATOMIC_SWAP_I8_POSTRA
    0U,	// B
    0U,	// BAL_BR
    0U,	// BAL_BR_MM
    536893669U,	// BEQLImmMacro
    536891521U,	// BGE
    536891521U,	// BGEImmMacro
    536893530U,	// BGEL
    536893530U,	// BGELImmMacro
    536895156U,	// BGEU
    536895156U,	// BGEUImmMacro
    536893700U,	// BGEUL
    536893700U,	// BGEULImmMacro
    536895037U,	// BGT
    536895037U,	// BGTImmMacro
    536893688U,	// BGTL
    536893688U,	// BGTLImmMacro
    536895282U,	// BGTU
    536895282U,	// BGTUImmMacro
    536893720U,	// BGTUL
    536893720U,	// BGTULImmMacro
    536891561U,	// BLE
    536891561U,	// BLEImmMacro
    536893536U,	// BLEL
    536893536U,	// BLELImmMacro
    536895174U,	// BLEU
    536895174U,	// BLEUImmMacro
    536893707U,	// BLEUL
    536893707U,	// BLEULImmMacro
    536895053U,	// BLT
    536895053U,	// BLTImmMacro
    536893694U,	// BLTL
    536893694U,	// BLTLImmMacro
    536895294U,	// BLTU
    536895294U,	// BLTUImmMacro
    536893727U,	// BLTUL
    536893727U,	// BLTULImmMacro
    536893542U,	// BNELImmMacro
    0U,	// BPOSGE32_PSEUDO
    0U,	// BSEL_D_PSEUDO
    0U,	// BSEL_FD_PSEUDO
    0U,	// BSEL_FW_PSEUDO
    0U,	// BSEL_H_PSEUDO
    0U,	// BSEL_W_PSEUDO
    0U,	// B_MM
    557807U,	// B_MMR6_Pseudo
    557807U,	// B_MM_Pseudo
    536894020U,	// BeqImm
    536891588U,	// BneImm
    1073764808U,	// BteqzT8CmpX16
    1073764241U,	// BteqzT8CmpiX16
    1073765970U,	// BteqzT8SltX16
    1073764271U,	// BteqzT8SltiX16
    1073766126U,	// BteqzT8SltiuX16
    1073766212U,	// BteqzT8SltuX16
    1610635720U,	// BtnezT8CmpX16
    1610635153U,	// BtnezT8CmpiX16
    1610636882U,	// BtnezT8SltX16
    1610635183U,	// BtnezT8SltiX16
    1610637038U,	// BtnezT8SltiuX16
    1610637124U,	// BtnezT8SltuX16
    0U,	// BuildPairF64
    0U,	// BuildPairF64_64
    26462U,	// CFTC1
    10592U,	// CONSTPOOL_ENTRY
    0U,	// COPY_FD_PSEUDO
    0U,	// COPY_FW_PSEUDO
    17885036U,	// CTTC1
    550788U,	// Constant32
    536893714U,	// DMULImmMacro
    536893714U,	// DMULMacro
    536893849U,	// DMULOMacro
    536895257U,	// DMULOUMacro
    536893653U,	// DROL
    536893653U,	// DROLImm
    536894187U,	// DROR
    536894187U,	// DRORImm
    536895419U,	// DSDivIMacro
    536895419U,	// DSDivMacro
    536893772U,	// DSRemIMacro
    536893772U,	// DSRemMacro
    536895327U,	// DUDivIMacro
    536895327U,	// DUDivMacro
    536895250U,	// DURemIMacro
    536895250U,	// DURemMacro
    0U,	// ERet
    0U,	// ExtractElementF64
    0U,	// ExtractElementF64_64
    0U,	// FABS_D
    0U,	// FABS_W
    0U,	// FEXP2_D_1_PSEUDO
    0U,	// FEXP2_W_1_PSEUDO
    0U,	// FILL_FD_PSEUDO
    0U,	// FILL_FW_PSEUDO
    2181060488U,	// GotPrologue16
    0U,	// INSERT_B_VIDX64_PSEUDO
    0U,	// INSERT_B_VIDX_PSEUDO
    0U,	// INSERT_D_VIDX64_PSEUDO
    0U,	// INSERT_D_VIDX_PSEUDO
    0U,	// INSERT_FD_PSEUDO
    0U,	// INSERT_FD_VIDX64_PSEUDO
    0U,	// INSERT_FD_VIDX_PSEUDO
    0U,	// INSERT_FW_PSEUDO
    0U,	// INSERT_FW_VIDX64_PSEUDO
    0U,	// INSERT_FW_VIDX_PSEUDO
    0U,	// INSERT_H_VIDX64_PSEUDO
    0U,	// INSERT_H_VIDX_PSEUDO
    0U,	// INSERT_W_VIDX64_PSEUDO
    0U,	// INSERT_W_VIDX_PSEUDO
    0U,	// JALR64Pseudo
    0U,	// JALRHB64Pseudo
    0U,	// JALRHBPseudo
    0U,	// JALRPseudo
    0U,	// JAL_MMR6
    546804U,	// JalOneReg
    22516U,	// JalTwoReg
    50358144U,	// LDMacro
    0U,	// LDR_D
    0U,	// LDR_W
    0U,	// LD_F16
    50348038U,	// LOAD_ACC128
    50348038U,	// LOAD_ACC64
    50348038U,	// LOAD_ACC64DSP
    50354654U,	// LOAD_CCOND_DSP
    0U,	// LONG_BRANCH_ADDiu
    0U,	// LONG_BRANCH_ADDiu2Op
    0U,	// LONG_BRANCH_DADDiu
    0U,	// LONG_BRANCH_DADDiu2Op
    0U,	// LONG_BRANCH_LUi
    0U,	// LONG_BRANCH_LUi2Op
    0U,	// LONG_BRANCH_LUi2Op_64
    72032U,	// LWM_MM
    17042U,	// LoadAddrImm32
    17063U,	// LoadAddrImm64
    50348690U,	// LoadAddrReg32
    50348711U,	// LoadAddrReg64
    22408U,	// LoadImm32
    22412U,	// LoadImm64
    19107U,	// LoadImmDoubleFGR
    19107U,	// LoadImmDoubleFGR_32
    19107U,	// LoadImmDoubleGPR
    23539U,	// LoadImmSingleFGR
    23539U,	// LoadImmSingleGPR
    1599118U,	// LwConstant32
    26588U,	// MFTACX
    536897344U,	// MFTC0
    26469U,	// MFTC1
    550833U,	// MFTDSP
    26566U,	// MFTGPR
    26446U,	// MFTHC1
    26517U,	// MFTHI
    26531U,	// MFTLO
    0U,	// MIPSeh_return32
    0U,	// MIPSeh_return64
    0U,	// MSA_FP_EXTEND_D_PSEUDO
    0U,	// MSA_FP_EXTEND_W_PSEUDO
    0U,	// MSA_FP_ROUND_D_PSEUDO
    0U,	// MSA_FP_ROUND_W_PSEUDO
    17885156U,	// MTTACX
    2752571207U,	// MTTC0
    17885043U,	// MTTC1
    550841U,	// MTTDSP
    17885134U,	// MTTGPR
    17885014U,	// MTTHC1
    17885084U,	// MTTHI
    17885098U,	// MTTLO
    536893715U,	// MULImmMacro
    536893850U,	// MULOMacro
    536895258U,	// MULOUMacro
    24157U,	// MultRxRy16
    86040157U,	// MultRxRyRz16
    24401U,	// MultuRxRy16
    86040401U,	// MultuRxRyRz16
    0U,	// NOP
    536894182U,	// NORImm
    536894182U,	// NORImm64
    0U,	// NOR_V_D_PSEUDO
    0U,	// NOR_V_H_PSEUDO
    0U,	// NOR_V_W_PSEUDO
    0U,	// OR_V_D_PSEUDO
    0U,	// OR_V_H_PSEUDO
    0U,	// OR_V_W_PSEUDO
    0U,	// PseudoCMPU_EQ_QB
    0U,	// PseudoCMPU_LE_QB
    0U,	// PseudoCMPU_LT_QB
    0U,	// PseudoCMP_EQ_PH
    0U,	// PseudoCMP_LE_PH
    0U,	// PseudoCMP_LT_PH
    16390U,	// PseudoCVT_D32_W
    16390U,	// PseudoCVT_D64_L
    16390U,	// PseudoCVT_D64_W
    16390U,	// PseudoCVT_S_L
    16390U,	// PseudoCVT_S_W
    0U,	// PseudoDMULT
    0U,	// PseudoDMULTu
    0U,	// PseudoDSDIV
    0U,	// PseudoDUDIV
    0U,	// PseudoD_SELECT_I
    0U,	// PseudoD_SELECT_I64
    0U,	// PseudoIndirectBranch
    0U,	// PseudoIndirectBranch64
    0U,	// PseudoIndirectBranch64R6
    0U,	// PseudoIndirectBranchR6
    0U,	// PseudoIndirectBranch_MM
    0U,	// PseudoIndirectBranch_MMR6
    0U,	// PseudoIndirectHazardBranch
    0U,	// PseudoIndirectHazardBranch64
    0U,	// PseudoIndrectHazardBranch64R6
    0U,	// PseudoIndrectHazardBranchR6
    0U,	// PseudoMADD
    0U,	// PseudoMADDU
    0U,	// PseudoMADDU_MM
    0U,	// PseudoMADD_MM
    0U,	// PseudoMFHI
    0U,	// PseudoMFHI64
    0U,	// PseudoMFHI_MM
    0U,	// PseudoMFLO
    0U,	// PseudoMFLO64
    0U,	// PseudoMFLO_MM
    0U,	// PseudoMSUB
    0U,	// PseudoMSUBU
    0U,	// PseudoMSUBU_MM
    0U,	// PseudoMSUB_MM
    0U,	// PseudoMTLOHI
    0U,	// PseudoMTLOHI64
    0U,	// PseudoMTLOHI_DSP
    0U,	// PseudoMTLOHI_MM
    0U,	// PseudoMULT
    0U,	// PseudoMULT_MM
    0U,	// PseudoMULTu
    0U,	// PseudoMULTu_MM
    0U,	// PseudoPICK_PH
    0U,	// PseudoPICK_QB
    0U,	// PseudoReturn
    0U,	// PseudoReturn64
    0U,	// PseudoSDIV
    0U,	// PseudoSELECTFP_F_D32
    0U,	// PseudoSELECTFP_F_D64
    0U,	// PseudoSELECTFP_F_I
    0U,	// PseudoSELECTFP_F_I64
    0U,	// PseudoSELECTFP_F_S
    0U,	// PseudoSELECTFP_T_D32
    0U,	// PseudoSELECTFP_T_D64
    0U,	// PseudoSELECTFP_T_I
    0U,	// PseudoSELECTFP_T_I64
    0U,	// PseudoSELECTFP_T_S
    0U,	// PseudoSELECT_D32
    0U,	// PseudoSELECT_D64
    0U,	// PseudoSELECT_I
    0U,	// PseudoSELECT_I64
    0U,	// PseudoSELECT_S
    536891300U,	// PseudoTRUNC_W_D
    536891300U,	// PseudoTRUNC_W_D32
    536894799U,	// PseudoTRUNC_W_S
    0U,	// PseudoUDIV
    536893654U,	// ROL
    536893654U,	// ROLImm
    536894188U,	// ROR
    536894188U,	// RORImm
    0U,	// RetRA
    0U,	// RetRA16
    50351255U,	// SDC1_M1
    0U,	// SDIV_MM_Pseudo
    50358156U,	// SDMacro
    536895420U,	// SDivIMacro
    536895420U,	// SDivMacro
    536897473U,	// SEQIMacro
    536897473U,	// SEQMacro
    536891526U,	// SGE
    536891526U,	// SGEImm
    536891526U,	// SGEImm64
    536895162U,	// SGEU
    536895162U,	// SGEUImm
    536895162U,	// SGEUImm64
    536895042U,	// SGTImm
    536895042U,	// SGTImm64
    536895288U,	// SGTUImm
    536895288U,	// SGTUImm64
    536891571U,	// SLE
    536891571U,	// SLEImm
    536891571U,	// SLEImm64
    536895180U,	// SLEU
    536895180U,	// SLEUImm
    536895180U,	// SLEUImm64
    536895058U,	// SLTImm64
    536895300U,	// SLTUImm64
    536897424U,	// SNEIMacro
    536897424U,	// SNEMacro
    0U,	// SNZ_B_PSEUDO
    0U,	// SNZ_D_PSEUDO
    0U,	// SNZ_H_PSEUDO
    0U,	// SNZ_V_PSEUDO
    0U,	// SNZ_W_PSEUDO
    536893773U,	// SRemIMacro
    536893773U,	// SRemMacro
    50348038U,	// STORE_ACC128
    50348038U,	// STORE_ACC64
    50348038U,	// STORE_ACC64DSP
    50354670U,	// STORE_CCOND_DSP
    0U,	// STR_D
    0U,	// STR_W
    0U,	// ST_F16
    72037U,	// SWM_MM
    0U,	// SZ_B_PSEUDO
    0U,	// SZ_D_PSEUDO
    0U,	// SZ_H_PSEUDO
    0U,	// SZ_V_PSEUDO
    0U,	// SZ_W_PSEUDO
    50348673U,	// SaaAddr
    50352145U,	// SaadAddr
    2713318U,	// SelBeqZ
    2713291U,	// SelBneZ
    3321977288U,	// SelTBteqZCmp
    3321976721U,	// SelTBteqZCmpi
    3321978450U,	// SelTBteqZSlt
    3321976751U,	// SelTBteqZSlti
    3321978606U,	// SelTBteqZSltiu
    3321978692U,	// SelTBteqZSltu
    3858848200U,	// SelTBtneZCmp
    3858847633U,	// SelTBtneZCmpi
    3858849362U,	// SelTBtneZSlt
    3858847663U,	// SelTBtneZSlti
    3858849518U,	// SelTBtneZSltiu
    3858849604U,	// SelTBtneZSltu
    119594578U,	// SltCCRxRy16
    119592879U,	// SltiCCRxImmX16
    119594734U,	// SltiuCCRxImmX16
    119594820U,	// SltuCCRxRy16
    119594820U,	// SltuRxRyRz16
    0U,	// TAILCALL
    0U,	// TAILCALL64R6REG
    0U,	// TAILCALLHB64R6REG
    0U,	// TAILCALLHBR6REG
    0U,	// TAILCALLR6REG
    0U,	// TAILCALLREG
    0U,	// TAILCALLREG64
    0U,	// TAILCALLREGHB
    0U,	// TAILCALLREGHB64
    0U,	// TAILCALLREG_MM
    0U,	// TAILCALLREG_MMR6
    0U,	// TAILCALL_MM
    0U,	// TAILCALL_MMR6
    0U,	// TRAP
    0U,	// TRAP_MM
    0U,	// UDIV_MM_Pseudo
    536895328U,	// UDivIMacro
    536895328U,	// UDivMacro
    536895251U,	// URemIMacro
    536895251U,	// URemMacro
    50353426U,	// Ulh
    50355922U,	// Ulhu
    50357901U,	// Ulw
    50353979U,	// Ush
    50357917U,	// Usw
    0U,	// XOR_V_D_PSEUDO
    0U,	// XOR_V_H_PSEUDO
    0U,	// XOR_V_W_PSEUDO
    22052U,	// ABSQ_S_PH
    22052U,	// ABSQ_S_PH_MM
    18197U,	// ABSQ_S_QB
    18197U,	// ABSQ_S_QB_MMR2
    25616U,	// ABSQ_S_W
    25616U,	// ABSQ_S_W_MM
    536891430U,	// ADD
    18483U,	// ADDIUPC
    18483U,	// ADDIUPC_MM
    18483U,	// ADDIUPC_MMR6
    22995U,	// ADDIUR1SP_MM
    536887674U,	// ADDIUR2_MM
    18923931U,	// ADDIUS5_MM
    547344U,	// ADDIUSP_MM
    536895200U,	// ADDIU_MMR6
    536892769U,	// ADDQH_PH
    536892769U,	// ADDQH_PH_MMR2
    536892886U,	// ADDQH_R_PH
    536892886U,	// ADDQH_R_PH_MMR2
    536896203U,	// ADDQH_R_W
    536896203U,	// ADDQH_R_W_MMR2
    536895806U,	// ADDQH_W
    536895806U,	// ADDQH_W_MMR2
    536892843U,	// ADDQ_PH
    536892843U,	// ADDQ_PH_MM
    536892942U,	// ADDQ_S_PH
    536892942U,	// ADDQ_S_PH_MM
    536896508U,	// ADDQ_S_W
    536896508U,	// ADDQ_S_W_MM
    536894967U,	// ADDR_PS64
    536889435U,	// ADDSC
    536889435U,	// ADDSC_MM
    536888059U,	// ADDS_A_B
    536889596U,	// ADDS_A_D
    536891696U,	// ADDS_A_H
    536895514U,	// ADDS_A_W
    536888527U,	// ADDS_S_B
    536890694U,	// ADDS_S_D
    536892253U,	// ADDS_S_H
    536896558U,	// ADDS_S_W
    536888742U,	// ADDS_U_B
    536891161U,	// ADDS_U_D
    536892531U,	// ADDS_U_H
    536896976U,	// ADDS_U_W
    536887894U,	// ADDU16_MM
    536887894U,	// ADDU16_MMR6
    536888977U,	// ADDUH_QB
    536888977U,	// ADDUH_QB_MMR2
    536889085U,	// ADDUH_R_QB
    536889085U,	// ADDUH_R_QB_MMR2
    536895129U,	// ADDU_MMR6
    536893041U,	// ADDU_PH
    536893041U,	// ADDU_PH_MMR2
    536889190U,	// ADDU_QB
    536889190U,	// ADDU_QB_MM
    536892986U,	// ADDU_S_PH
    536892986U,	// ADDU_S_PH_MMR2
    536889131U,	// ADDU_S_QB
    536889131U,	// ADDU_S_QB_MM
    536888308U,	// ADDVI_B
    536890116U,	// ADDVI_D
    536891912U,	// ADDVI_H
    536895939U,	// ADDVI_W
    536888820U,	// ADDV_B
    536891251U,	// ADDV_D
    536892609U,	// ADDV_H
    536897076U,	// ADDV_W
    536889474U,	// ADDWC
    536889474U,	// ADDWC_MM
    536888041U,	// ADD_A_B
    536889577U,	// ADD_A_D
    536891678U,	// ADD_A_H
    536895495U,	// ADD_A_W
    536891430U,	// ADD_MM
    536891430U,	// ADD_MMR6
    536893262U,	// ADDi
    536893262U,	// ADDi_MM
    536895200U,	// ADDiu
    536895200U,	// ADDiu_MM
    536895129U,	// ADDu
    536895129U,	// ADDu_MM
    536893803U,	// ALIGN
    536893803U,	// ALIGN_MMR6
    18475U,	// ALUIPC
    18475U,	// ALUIPC_MMR6
    536891459U,	// AND
    20021705U,	// AND16_MM
    20021705U,	// AND16_MMR6
    536891459U,	// AND64
    536887774U,	// ANDI16_MM
    536887774U,	// ANDI16_MMR6
    536888167U,	// ANDI_B
    536893268U,	// ANDI_MMR6
    536891459U,	// AND_MM
    536891459U,	// AND_MMR6
    536895339U,	// AND_V
    536893268U,	// ANDi
    536893268U,	// ANDi64
    536893268U,	// ANDi_MM
    536891473U,	// APPEND
    536891473U,	// APPEND_MMR2
    536888421U,	// ASUB_S_B
    536890524U,	// ASUB_S_D
    536892085U,	// ASUB_S_H
    536896338U,	// ASUB_S_W
    536888636U,	// ASUB_U_B
    536890991U,	// ASUB_U_D
    536892373U,	// ASUB_U_H
    536896806U,	// ASUB_U_W
    536893372U,	// AUI
    18468U,	// AUIPC
    18468U,	// AUIPC_MMR6
    536893372U,	// AUI_MMR6
    536888507U,	// AVER_S_B
    536890674U,	// AVER_S_D
    536892223U,	// AVER_S_H
    536896538U,	// AVER_S_W
    536888722U,	// AVER_U_B
    536891141U,	// AVER_U_D
    536892511U,	// AVER_U_H
    536896956U,	// AVER_U_W
    536888449U,	// AVE_S_B
    536890606U,	// AVE_S_D
    536892155U,	// AVE_S_H
    536896420U,	// AVE_S_W
    536888664U,	// AVE_U_B
    536891073U,	// AVE_U_D
    536892443U,	// AVE_U_H
    536896888U,	// AVE_U_W
    24288U,	// AddiuRxImmX16
    3694304U,	// AddiuRxPcImmX16
    33578720U,	// AddiuRxRxImm16
    33578720U,	// AddiuRxRxImmX16
    134242016U,	// AddiuRxRyOffMemX16
    4220724U,	// AddiuSpImm16
    550708U,	// AddiuSpImmX16
    536895129U,	// AdduRxRyRz16
    33574979U,	// AndRxRxRy16
    557477U,	// B16_MM
    536895128U,	// BADDu
    563183U,	// BAL
    559061U,	// BALC
    559061U,	// BALC_MMR6
    536893802U,	// BALIGN
    536893802U,	// BALIGN_MMR2
    151011407U,	// BBIT0
    151011539U,	// BBIT032
    151011532U,	// BBIT1
    151011548U,	// BBIT132
    559040U,	// BC
    557482U,	// BC16_MMR6
    167798780U,	// BC1EQZ
    167790768U,	// BC1EQZC_MMR6
    167792903U,	// BC1F
    167794796U,	// BC1FL
    167792903U,	// BC1F_MM
    167798764U,	// BC1NEZ
    167790743U,	// BC1NEZC_MMR6
    167796279U,	// BC1T
    167794929U,	// BC1TL
    167796279U,	// BC1T_MM
    167798788U,	// BC2EQZ
    167790777U,	// BC2EQZC_MMR6
    167798772U,	// BC2NEZ
    167790752U,	// BC2NEZC_MMR6
    536888236U,	// BCLRI_B
    536890060U,	// BCLRI_D
    536891856U,	// BCLRI_H
    536895883U,	// BCLRI_W
    536888388U,	// BCLR_B
    536890448U,	// BCLR_D
    536892052U,	// BCLR_H
    536896254U,	// BCLR_W
    559040U,	// BC_MMR6
    536894020U,	// BEQ
    536894020U,	// BEQ64
    536889417U,	// BEQC
    536889417U,	// BEQC64
    536889417U,	// BEQC_MMR6
    536893669U,	// BEQL
    167789177U,	// BEQZ16_MM
    167790589U,	// BEQZALC
    167790589U,	// BEQZALC_MMR6
    167790786U,	// BEQZC
    167788992U,	// BEQZC16_MMR6
    167790786U,	// BEQZC64
    167790786U,	// BEQZC_MM
    167790786U,	// BEQZC_MMR6
    536894020U,	// BEQ_MM
    536889284U,	// BGEC
    536889284U,	// BGEC64
    536889284U,	// BGEC_MMR6
    536889448U,	// BGEUC
    536889448U,	// BGEUC64
    536889448U,	// BGEUC_MMR6
    167798463U,	// BGEZ
    167798463U,	// BGEZ64
    167794681U,	// BGEZAL
    167790562U,	// BGEZALC
    167790562U,	// BGEZALC_MMR6
    167794877U,	// BGEZALL
    167796145U,	// BGEZALS_MM
    167794681U,	// BGEZAL_MM
    167790729U,	// BGEZC
    167790729U,	// BGEZC64
    167790729U,	// BGEZC_MMR6
    167794992U,	// BGEZL
    167798463U,	// BGEZ_MM
    167798523U,	// BGTZ
    167798523U,	// BGTZ64
    167790598U,	// BGTZALC
    167790598U,	// BGTZALC_MMR6
    167790793U,	// BGTZC
    167790793U,	// BGTZC64
    167790793U,	// BGTZC_MMR6
    167795006U,	// BGTZL
    167798523U,	// BGTZ_MM
    570442641U,	// BINSLI_B
    570444465U,	// BINSLI_D
    570446261U,	// BINSLI_H
    570450288U,	// BINSLI_W
    570442788U,	// BINSL_B
    570444665U,	// BINSL_D
    570446375U,	// BINSL_H
    570450446U,	// BINSL_W
    570442702U,	// BINSRI_B
    570444510U,	// BINSRI_D
    570446306U,	// BINSRI_H
    570450333U,	// BINSRI_W
    570442836U,	// BINSR_B
    570444930U,	// BINSR_D
    570446500U,	// BINSR_H
    570450736U,	// BINSR_W
    24499U,	// BITREV
    24499U,	// BITREV_MM
    22945U,	// BITSWAP
    22945U,	// BITSWAP_MMR6
    167798469U,	// BLEZ
    167798469U,	// BLEZ64
    167790571U,	// BLEZALC
    167790571U,	// BLEZALC_MMR6
    167790736U,	// BLEZC
    167790736U,	// BLEZC64
    167790736U,	// BLEZC_MMR6
    167794999U,	// BLEZL
    167798469U,	// BLEZ_MM
    536889442U,	// BLTC
    536889442U,	// BLTC64
    536889442U,	// BLTC_MMR6
    536889455U,	// BLTUC
    536889455U,	// BLTUC64
    536889455U,	// BLTUC_MMR6
    167798529U,	// BLTZ
    167798529U,	// BLTZ64
    167794689U,	// BLTZAL
    167790607U,	// BLTZALC
    167790607U,	// BLTZALC_MMR6
    167794886U,	// BLTZALL
    167796154U,	// BLTZALS_MM
    167794689U,	// BLTZAL_MM
    167790800U,	// BLTZC
    167790800U,	// BLTZC64
    167790800U,	// BLTZC_MMR6
    167795013U,	// BLTZL
    167798529U,	// BLTZ_MM
    570442757U,	// BMNZI_B
    570449828U,	// BMNZ_V
    570442749U,	// BMZI_B
    570449814U,	// BMZ_V
    536891588U,	// BNE
    536891588U,	// BNE64
    536889290U,	// BNEC
    536889290U,	// BNEC64
    536889290U,	// BNEC_MMR6
    536888175U,	// BNEGI_B
    536890008U,	// BNEGI_D
    536891804U,	// BNEGI_H
    536895831U,	// BNEGI_W
    536888143U,	// BNEG_B
    536889984U,	// BNEG_D
    536891780U,	// BNEG_H
    536895726U,	// BNEG_W
    536893542U,	// BNEL
    167789169U,	// BNEZ16_MM
    167790580U,	// BNEZALC
    167790580U,	// BNEZALC_MMR6
    167790761U,	// BNEZC
    167788983U,	// BNEZC16_MMR6
    167790761U,	// BNEZC64
    167790761U,	// BNEZC_MM
    167790761U,	// BNEZC_MMR6
    536891588U,	// BNE_MM
    536889462U,	// BNVC
    536889462U,	// BNVC_MMR6
    167790108U,	// BNZ_B
    167792624U,	// BNZ_D
    167793897U,	// BNZ_H
    167796637U,	// BNZ_V
    167798389U,	// BNZ_W
    536889468U,	// BOVC
    536889468U,	// BOVC_MMR6
    557293U,	// BPOSGE32
    559029U,	// BPOSGE32C_MMR3
    557293U,	// BPOSGE32_MM
    184670160U,	// BREAK
    131572U,	// BREAK16_MM
    131572U,	// BREAK16_MMR6
    184670160U,	// BREAK_MM
    184670160U,	// BREAK_MMR6
    570442616U,	// BSELI_B
    570449786U,	// BSEL_V
    536888290U,	// BSETI_B
    536890098U,	// BSETI_D
    536891894U,	// BSETI_H
    536895921U,	// BSETI_W
    536888604U,	// BSET_B
    536890810U,	// BSET_D
    536892341U,	// BSET_H
    536896712U,	// BSET_W
    167790102U,	// BZ_B
    167792608U,	// BZ_D
    167793891U,	// BZ_H
    167796624U,	// BZ_V
    167798383U,	// BZ_W
    704669414U,	// BeqzRxImm16
    167798502U,	// BeqzRxImmX16
    4227823U,	// Bimm16
    557807U,	// BimmX16
    704669387U,	// BnezRxImm16
    167798475U,	// BnezRxImmX16
    10403U,	// Break16
    4744948U,	// Bteqz16
    550644U,	// BteqzX16
    4744921U,	// Btnez16
    550617U,	// BtnezX16
    5394576U,	// CACHE
    5394546U,	// CACHEE
    5394546U,	// CACHEE_MM
    5394576U,	// CACHE_MM
    5394576U,	// CACHE_MMR6
    5394576U,	// CACHE_R6
    19235U,	// CEIL_L_D64
    19235U,	// CEIL_L_D_MMR6
    23567U,	// CEIL_L_S
    23567U,	// CEIL_L_S_MMR6
    20410U,	// CEIL_W_D32
    20410U,	// CEIL_W_D64
    20410U,	// CEIL_W_D_MMR6
    20410U,	// CEIL_W_MM
    23909U,	// CEIL_W_S
    23909U,	// CEIL_W_S_MM
    23909U,	// CEIL_W_S_MMR6
    536888219U,	// CEQI_B
    536890043U,	// CEQI_D
    536891839U,	// CEQI_H
    536895866U,	// CEQI_W
    536888373U,	// CEQ_B
    536890355U,	// CEQ_D
    536892030U,	// CEQ_H
    536896142U,	// CEQ_W
    16482U,	// CFC1
    16482U,	// CFC1_MM
    16698U,	// CFC2_MM
    17113U,	// CFCMSA
    536894915U,	// CINS
    536887582U,	// CINS32
    536894915U,	// CINS64_32
    536894915U,	// CINS_i32
    19880U,	// CLASS_D
    19880U,	// CLASS_D_MMR6
    23760U,	// CLASS_S
    23760U,	// CLASS_S_MMR6
    536888458U,	// CLEI_S_B
    536890615U,	// CLEI_S_D
    536892164U,	// CLEI_S_H
    536896429U,	// CLEI_S_W
    536888673U,	// CLEI_U_B
    536891082U,	// CLEI_U_D
    536892452U,	// CLEI_U_H
    536896897U,	// CLEI_U_W
    536888440U,	// CLE_S_B
    536890597U,	// CLE_S_D
    536892146U,	// CLE_S_H
    536896411U,	// CLE_S_W
    536888655U,	// CLE_U_B
    536891064U,	// CLE_U_D
    536892434U,	// CLE_U_H
    536896879U,	// CLE_U_W
    22913U,	// CLO
    22913U,	// CLO_MM
    22913U,	// CLO_MMR6
    22913U,	// CLO_R6
    536888478U,	// CLTI_S_B
    536890635U,	// CLTI_S_D
    536892184U,	// CLTI_S_H
    536896449U,	// CLTI_S_W
    536888693U,	// CLTI_U_B
    536891102U,	// CLTI_U_D
    536892472U,	// CLTI_U_H
    536896917U,	// CLTI_U_W
    536888546U,	// CLT_S_B
    536890713U,	// CLT_S_D
    536892272U,	// CLT_S_H
    536896577U,	// CLT_S_W
    536888773U,	// CLT_U_B
    536891192U,	// CLT_U_D
    536892562U,	// CLT_U_H
    536897007U,	// CLT_U_W
    26337U,	// CLZ
    26337U,	// CLZ_MM
    26337U,	// CLZ_MMR6
    26337U,	// CLZ_R6
    536889023U,	// CMPGDU_EQ_QB
    536889023U,	// CMPGDU_EQ_QB_MMR2
    536888928U,	// CMPGDU_LE_QB
    536888928U,	// CMPGDU_LE_QB_MMR2
    536889142U,	// CMPGDU_LT_QB
    536889142U,	// CMPGDU_LT_QB_MMR2
    536889037U,	// CMPGU_EQ_QB
    536889037U,	// CMPGU_EQ_QB_MM
    536888942U,	// CMPGU_LE_QB
    536888942U,	// CMPGU_LE_QB_MM
    536889156U,	// CMPGU_LT_QB
    536889156U,	// CMPGU_LT_QB_MM
    18138U,	// CMPU_EQ_QB
    18138U,	// CMPU_EQ_QB_MM
    18043U,	// CMPU_LE_QB
    18043U,	// CMPU_LE_QB_MM
    18257U,	// CMPU_LT_QB
    18257U,	// CMPU_LT_QB_MM
    536889905U,	// CMP_AF_D_MMR6
    536894389U,	// CMP_AF_S_MMR6
    536890344U,	// CMP_EQ_D
    536890344U,	// CMP_EQ_D_MMR6
    21940U,	// CMP_EQ_PH
    21940U,	// CMP_EQ_PH_MM
    536894593U,	// CMP_EQ_S
    536894593U,	// CMP_EQ_S_MMR6
    536889905U,	// CMP_F_D
    536894389U,	// CMP_F_S
    536889749U,	// CMP_LE_D
    536889749U,	// CMP_LE_D_MMR6
    21836U,	// CMP_LE_PH
    21836U,	// CMP_LE_PH_MM
    536894310U,	// CMP_LE_S
    536894310U,	// CMP_LE_S_MMR6
    536890835U,	// CMP_LT_D
    536890835U,	// CMP_LT_D_MMR6
    22109U,	// CMP_LT_PH
    22109U,	// CMP_LT_PH_MM
    536894698U,	// CMP_LT_S
    536894698U,	// CMP_LT_S_MMR6
    536889923U,	// CMP_SAF_D
    536889923U,	// CMP_SAF_D_MMR6
    536894399U,	// CMP_SAF_S
    536894399U,	// CMP_SAF_S_MMR6
    536890371U,	// CMP_SEQ_D
    536890371U,	// CMP_SEQ_D_MMR6
    536894612U,	// CMP_SEQ_S
    536894612U,	// CMP_SEQ_S_MMR6
    536889786U,	// CMP_SLE_D
    536889786U,	// CMP_SLE_D_MMR6
    536894339U,	// CMP_SLE_S
    536894339U,	// CMP_SLE_S_MMR6
    536890862U,	// CMP_SLT_D
    536890862U,	// CMP_SLT_D_MMR6
    536894717U,	// CMP_SLT_S
    536894717U,	// CMP_SLT_S_MMR6
    536890419U,	// CMP_SUEQ_D
    536890419U,	// CMP_SUEQ_D_MMR6
    536894643U,	// CMP_SUEQ_S
    536894643U,	// CMP_SUEQ_S_MMR6
    536889834U,	// CMP_SULE_D
    536889834U,	// CMP_SULE_D_MMR6
    536894370U,	// CMP_SULE_S
    536894370U,	// CMP_SULE_S_MMR6
    536890910U,	// CMP_SULT_D
    536890910U,	// CMP_SULT_D_MMR6
    536894748U,	// CMP_SULT_S
    536894748U,	// CMP_SULT_S_MMR6
    536890292U,	// CMP_SUN_D
    536890292U,	// CMP_SUN_D_MMR6
    536894557U,	// CMP_SUN_S
    536894557U,	// CMP_SUN_S_MMR6
    536890399U,	// CMP_UEQ_D
    536890399U,	// CMP_UEQ_D_MMR6
    536894632U,	// CMP_UEQ_S
    536894632U,	// CMP_UEQ_S_MMR6
    536889814U,	// CMP_ULE_D
    536889814U,	// CMP_ULE_D_MMR6
    536894359U,	// CMP_ULE_S
    536894359U,	// CMP_ULE_S_MMR6
    536890890U,	// CMP_ULT_D
    536890890U,	// CMP_ULT_D_MMR6
    536894737U,	// CMP_ULT_S
    536894737U,	// CMP_ULT_S_MMR6
    536890274U,	// CMP_UN_D
    536890274U,	// CMP_UN_D_MMR6
    536894547U,	// CMP_UN_S
    536894547U,	// CMP_UN_S_MMR6
    1073759497U,	// COPY_S_B
    1073761686U,	// COPY_S_D
    1073763234U,	// COPY_S_H
    1073767561U,	// COPY_S_W
    1073759712U,	// COPY_U_B
    1073763501U,	// COPY_U_H
    1073767968U,	// COPY_U_W
    536888867U,	// CRC32B
    536888875U,	// CRC32CB
    536891415U,	// CRC32CD
    536892676U,	// CRC32CH
    536897156U,	// CRC32CW
    536891401U,	// CRC32D
    536892656U,	// CRC32H
    536897148U,	// CRC32W
    17875069U,	// CTC1
    17875069U,	// CTC1_MM
    17875285U,	// CTC2_MM
    17121U,	// CTCMSA
    23363U,	// CVT_D32_S
    23363U,	// CVT_D32_S_MM
    24662U,	// CVT_D32_W
    24662U,	// CVT_D32_W_MM
    22493U,	// CVT_D64_L
    23363U,	// CVT_D64_S
    23363U,	// CVT_D64_S_MM
    24662U,	// CVT_D64_W
    24662U,	// CVT_D64_W_MM
    22493U,	// CVT_D_L_MMR6
    19256U,	// CVT_L_D64
    19256U,	// CVT_L_D64_MM
    19256U,	// CVT_L_D_MMR6
    23588U,	// CVT_L_S
    23588U,	// CVT_L_S_MM
    23588U,	// CVT_L_S_MMR6
    26258U,	// CVT_PS_PW64
    536894662U,	// CVT_PS_S64
    24089U,	// CVT_PW_PS64
    19603U,	// CVT_S_D32
    19603U,	// CVT_S_D32_MM
    19603U,	// CVT_S_D64
    19603U,	// CVT_S_D64_MM
    22502U,	// CVT_S_L
    22502U,	// CVT_S_L_MMR6
    22747U,	// CVT_S_PL64
    24353U,	// CVT_S_PU64
    25417U,	// CVT_S_W
    25417U,	// CVT_S_W_MM
    25417U,	// CVT_S_W_MMR6
    20431U,	// CVT_W_D32
    20431U,	// CVT_W_D32_MM
    20431U,	// CVT_W_D64
    20431U,	// CVT_W_D64_MM
    23930U,	// CVT_W_S
    23930U,	// CVT_W_S_MM
    23930U,	// CVT_W_S_MMR6
    536890336U,	// C_EQ_D32
    536890336U,	// C_EQ_D32_MM
    536890336U,	// C_EQ_D64
    536890336U,	// C_EQ_D64_MM
    536894585U,	// C_EQ_S
    536894585U,	// C_EQ_S_MM
    536889898U,	// C_F_D32
    536889898U,	// C_F_D32_MM
    536889898U,	// C_F_D64
    536889898U,	// C_F_D64_MM
    536894382U,	// C_F_S
    536894382U,	// C_F_S_MM
    536889741U,	// C_LE_D32
    536889741U,	// C_LE_D32_MM
    536889741U,	// C_LE_D64
    536889741U,	// C_LE_D64_MM
    536894302U,	// C_LE_S
    536894302U,	// C_LE_S_MM
    536890827U,	// C_LT_D32
    536890827U,	// C_LT_D32_MM
    536890827U,	// C_LT_D64
    536890827U,	// C_LT_D64_MM
    536894690U,	// C_LT_S
    536894690U,	// C_LT_S_MM
    536889732U,	// C_NGE_D32
    536889732U,	// C_NGE_D32_MM
    536889732U,	// C_NGE_D64
    536889732U,	// C_NGE_D64_MM
    536894293U,	// C_NGE_S
    536894293U,	// C_NGE_S_MM
    536889767U,	// C_NGLE_D32
    536889767U,	// C_NGLE_D32_MM
    536889767U,	// C_NGLE_D64
    536889767U,	// C_NGLE_D64_MM
    536894320U,	// C_NGLE_S
    536894320U,	// C_NGLE_S_MM
    536890184U,	// C_NGL_D32
    536890184U,	// C_NGL_D32_MM
    536890184U,	// C_NGL_D64
    536890184U,	// C_NGL_D64_MM
    536894516U,	// C_NGL_S
    536894516U,	// C_NGL_S_MM
    536890818U,	// C_NGT_D32
    536890818U,	// C_NGT_D32_MM
    536890818U,	// C_NGT_D64
    536890818U,	// C_NGT_D64_MM
    536894681U,	// C_NGT_S
    536894681U,	// C_NGT_S_MM
    536889777U,	// C_OLE_D32
    536889777U,	// C_OLE_D32_MM
    536889777U,	// C_OLE_D64
    536889777U,	// C_OLE_D64_MM
    536894330U,	// C_OLE_S
    536894330U,	// C_OLE_S_MM
    536890853U,	// C_OLT_D32
    536890853U,	// C_OLT_D32_MM
    536890853U,	// C_OLT_D64
    536890853U,	// C_OLT_D64_MM
    536894708U,	// C_OLT_S
    536894708U,	// C_OLT_S_MM
    536890362U,	// C_SEQ_D32
    536890362U,	// C_SEQ_D32_MM
    536890362U,	// C_SEQ_D64
    536890362U,	// C_SEQ_D64_MM
    536894603U,	// C_SEQ_S
    536894603U,	// C_SEQ_S_MM
    536889968U,	// C_SF_D32
    536889968U,	// C_SF_D32_MM
    536889968U,	// C_SF_D64
    536889968U,	// C_SF_D64_MM
    536894428U,	// C_SF_S
    536894428U,	// C_SF_S_MM
    536890390U,	// C_UEQ_D32
    536890390U,	// C_UEQ_D32_MM
    536890390U,	// C_UEQ_D64
    536890390U,	// C_UEQ_D64_MM
    536894623U,	// C_UEQ_S
    536894623U,	// C_UEQ_S_MM
    536889805U,	// C_ULE_D32
    536889805U,	// C_ULE_D32_MM
    536889805U,	// C_ULE_D64
    536889805U,	// C_ULE_D64_MM
    536894350U,	// C_ULE_S
    536894350U,	// C_ULE_S_MM
    536890881U,	// C_ULT_D32
    536890881U,	// C_ULT_D32_MM
    536890881U,	// C_ULT_D64
    536890881U,	// C_ULT_D64_MM
    536894728U,	// C_ULT_S
    536894728U,	// C_ULT_S_MM
    536890266U,	// C_UN_D32
    536890266U,	// C_UN_D32_MM
    536890266U,	// C_UN_D64
    536890266U,	// C_UN_D64_MM
    536894539U,	// C_UN_S
    536894539U,	// C_UN_S_MM
    22984U,	// CmpRxRy16
    1610635153U,	// CmpiRxImm16
    22417U,	// CmpiRxImmX16
    536891429U,	// DADD
    536893261U,	// DADDi
    536895199U,	// DADDiu
    536895135U,	// DADDu
    536893292U,	// DAHI
    536893810U,	// DALIGN
    536893353U,	// DATI
    536893371U,	// DAUI
    22944U,	// DBITSWAP
    22912U,	// DCLO
    22912U,	// DCLO_R6
    26336U,	// DCLZ
    26336U,	// DCLZ_R6
    536895419U,	// DDIV
    536895327U,	// DDIVU
    10637U,	// DERET
    10637U,	// DERET_MM
    10637U,	// DERET_MMR6
    536895103U,	// DEXT
    536897494U,	// DEXT64_32
    536893785U,	// DEXTM
    536895320U,	// DEXTU
    546640U,	// DI
    536894921U,	// DINS
    536893778U,	// DINSM
    536895275U,	// DINSU
    536895420U,	// DIV
    536895328U,	// DIVU
    536895328U,	// DIVU_MMR6
    536895420U,	// DIV_MMR6
    536888567U,	// DIV_S_B
    536890756U,	// DIV_S_D
    536892293U,	// DIV_S_H
    536896620U,	// DIV_S_W
    536888782U,	// DIV_U_B
    536891223U,	// DIV_U_D
    536892571U,	// DIV_U_H
    536897038U,	// DIV_U_W
    546640U,	// DI_MM
    546640U,	// DI_MMR6
    536888019U,	// DLSA
    536888019U,	// DLSA_R6
    536887297U,	// DMFC0
    16488U,	// DMFC1
    536887616U,	// DMFC2
    201343296U,	// DMFC2_OCTEON
    536887304U,	// DMFGC0
    536891481U,	// DMOD
    536895149U,	// DMODU
    548451U,	// DMT
    2752561206U,	// DMTC0
    17875075U,	// DMTC1
    2752561499U,	// DMTC2
    201343323U,	// DMTC2_OCTEON
    2752561184U,	// DMTGC0
    536893248U,	// DMUH
    536895192U,	// DMUHU
    536893714U,	// DMUL
    24156U,	// DMULT
    24400U,	// DMULTu
    536895236U,	// DMULU
    536893714U,	// DMUL_R6
    536890664U,	// DOTP_S_D
    536892213U,	// DOTP_S_H
    536896488U,	// DOTP_S_W
    536891131U,	// DOTP_U_D
    536892501U,	// DOTP_U_H
    536896946U,	// DOTP_U_W
    570445009U,	// DPADD_S_D
    570446558U,	// DPADD_S_H
    570450823U,	// DPADD_S_W
    570445476U,	// DPADD_U_D
    570446846U,	// DPADD_U_H
    570451291U,	// DPADD_U_W
    536893100U,	// DPAQX_SA_W_PH
    536893100U,	// DPAQX_SA_W_PH_MMR2
    536893183U,	// DPAQX_S_W_PH
    536893183U,	// DPAQX_S_W_PH_MMR2
    536895948U,	// DPAQ_SA_L_W
    536895948U,	// DPAQ_SA_L_W_MM
    536893142U,	// DPAQ_S_W_PH
    536893142U,	// DPAQ_S_W_PH_MM
    536893449U,	// DPAU_H_QBL
    536893449U,	// DPAU_H_QBL_MM
    536894035U,	// DPAU_H_QBR
    536894035U,	// DPAU_H_QBR_MM
    536893221U,	// DPAX_W_PH
    536893221U,	// DPAX_W_PH_MMR2
    536893090U,	// DPA_W_PH
    536893090U,	// DPA_W_PH_MMR2
    22989U,	// DPOP
    536893115U,	// DPSQX_SA_W_PH
    536893115U,	// DPSQX_SA_W_PH_MMR2
    536893197U,	// DPSQX_S_W_PH
    536893197U,	// DPSQX_S_W_PH_MMR2
    536895961U,	// DPSQ_SA_L_W
    536895961U,	// DPSQ_SA_L_W_MM
    536893170U,	// DPSQ_S_W_PH
    536893170U,	// DPSQ_S_W_PH_MM
    570444976U,	// DPSUB_S_D
    570446537U,	// DPSUB_S_H
    570450790U,	// DPSUB_S_W
    570445443U,	// DPSUB_U_D
    570446825U,	// DPSUB_U_H
    570451258U,	// DPSUB_U_W
    536893461U,	// DPSU_H_QBL
    536893461U,	// DPSU_H_QBL_MM
    536894047U,	// DPSU_H_QBR
    536894047U,	// DPSU_H_QBR_MM
    536893232U,	// DPSX_W_PH
    536893232U,	// DPSX_W_PH_MMR2
    536893211U,	// DPS_W_PH
    536893211U,	// DPS_W_PH_MMR2
    536894220U,	// DROTR
    536887573U,	// DROTR32
    536895463U,	// DROTRV
    21752U,	// DSBH
    26407U,	// DSDIV
    20529U,	// DSHD
    536893647U,	// DSLL
    536887543U,	// DSLL32
    2147506383U,	// DSLL64_32
    536895425U,	// DSLLV
    536888013U,	// DSRA
    536887525U,	// DSRA32
    536895404U,	// DSRAV
    536893675U,	// DSRL
    536887551U,	// DSRL32
    536895432U,	// DSRLV
    536889257U,	// DSUB
    536895114U,	// DSUBu
    26393U,	// DUDIV
    547376U,	// DVP
    544979U,	// DVPE
    547376U,	// DVP_MMR6
    26408U,	// DivRxRy16
    26394U,	// DivuRxRy16
    10531U,	// EHB
    10531U,	// EHB_MM
    10531U,	// EHB_MMR6
    546652U,	// EI
    546652U,	// EI_MM
    546652U,	// EI_MMR6
    548456U,	// EMT
    10638U,	// ERET
    10535U,	// ERETNC
    10535U,	// ERETNC_MMR6
    10638U,	// ERET_MM
    10638U,	// ERET_MMR6
    547381U,	// EVP
    544985U,	// EVPE
    547381U,	// EVP_MMR6
    536895104U,	// EXT
    536893994U,	// EXTP
    536893873U,	// EXTPDP
    536895447U,	// EXTPDPV
    536895447U,	// EXTPDPV_MM
    536893873U,	// EXTPDP_MM
    536895456U,	// EXTPV
    536895456U,	// EXTPV_MM
    536893994U,	// EXTP_MM
    536896681U,	// EXTRV_RS_W
    536896681U,	// EXTRV_RS_W_MM
    536896235U,	// EXTRV_R_W
    536896235U,	// EXTRV_R_W_MM
    536892302U,	// EXTRV_S_H
    536892302U,	// EXTRV_S_H_MM
    536897118U,	// EXTRV_W
    536897118U,	// EXTRV_W_MM
    536896670U,	// EXTR_RS_W
    536896670U,	// EXTR_RS_W_MM
    536896214U,	// EXTR_R_W
    536896214U,	// EXTR_R_W_MM
    536892233U,	// EXTR_S_H
    536892233U,	// EXTR_S_H_MM
    536896313U,	// EXTR_W
    536896313U,	// EXTR_W_MM
    536895019U,	// EXTS
    536887590U,	// EXTS32
    536895104U,	// EXT_MM
    536895104U,	// EXT_MMR6
    19872U,	// FABS_D32
    19872U,	// FABS_D32_MM
    19872U,	// FABS_D64
    19872U,	// FABS_D64_MM
    23743U,	// FABS_S
    23743U,	// FABS_S_MM
    536889681U,	// FADD_D
    536889682U,	// FADD_D32
    536889682U,	// FADD_D32_MM
    536889682U,	// FADD_D64
    536889682U,	// FADD_D64_MM
    536894935U,	// FADD_PS64
    536894286U,	// FADD_S
    536894286U,	// FADD_S_MM
    570448718U,	// FADD_S_MMR6
    536895583U,	// FADD_W
    536889915U,	// FCAF_D
    536895702U,	// FCAF_W
    536890354U,	// FCEQ_D
    536896141U,	// FCEQ_W
    19879U,	// FCLASS_D
    25781U,	// FCLASS_W
    536889759U,	// FCLE_D
    536895625U,	// FCLE_W
    536890845U,	// FCLT_D
    536896720U,	// FCLT_W
    5941291U,	// FCMP_D32
    5941291U,	// FCMP_D32_MM
    5941291U,	// FCMP_D64
    6465579U,	// FCMP_S32
    6465579U,	// FCMP_S32_MM
    536889855U,	// FCNE_D
    536895659U,	// FCNE_W
    536890464U,	// FCOR_D
    536896270U,	// FCOR_W
    536890410U,	// FCUEQ_D
    536896157U,	// FCUEQ_W
    536889825U,	// FCULE_D
    536895641U,	// FCULE_W
    536890901U,	// FCULT_D
    536896736U,	// FCULT_W
    536889871U,	// FCUNE_D
    536895675U,	// FCUNE_W
    536890284U,	// FCUN_D
    536896047U,	// FCUN_W
    536891277U,	// FDIV_D
    536891278U,	// FDIV_D32
    536891278U,	// FDIV_D32_MM
    536891278U,	// FDIV_D64
    536891278U,	// FDIV_D64_MM
    536894785U,	// FDIV_S
    536894785U,	// FDIV_S_MM
    570449217U,	// FDIV_S_MMR6
    536897102U,	// FDIV_W
    536891960U,	// FEXDO_H
    536896063U,	// FEXDO_W
    536889568U,	// FEXP2_D
    536895486U,	// FEXP2_W
    19296U,	// FEXUPL_D
    25077U,	// FEXUPL_W
    19568U,	// FEXUPR_D
    25374U,	// FEXUPR_W
    19810U,	// FFINT_S_D
    25674U,	// FFINT_S_W
    20289U,	// FFINT_U_D
    26104U,	// FFINT_U_W
    19306U,	// FFQL_D
    25087U,	// FFQL_W
    19578U,	// FFQR_D
    25384U,	// FFQR_W
    17422U,	// FILL_B
    19281U,	// FILL_D
    21009U,	// FILL_H
    25062U,	// FILL_W
    18647U,	// FLOG2_D
    24565U,	// FLOG2_W
    19245U,	// FLOOR_L_D64
    19245U,	// FLOOR_L_D_MMR6
    23577U,	// FLOOR_L_S
    23577U,	// FLOOR_L_S_MMR6
    20420U,	// FLOOR_W_D32
    20420U,	// FLOOR_W_D64
    20420U,	// FLOOR_W_D_MMR6
    20420U,	// FLOOR_W_MM
    23919U,	// FLOOR_W_S
    23919U,	// FLOOR_W_S_MM
    23919U,	// FLOOR_W_S_MMR6
    570444121U,	// FMADD_D
    570450023U,	// FMADD_W
    536889606U,	// FMAX_A_D
    536895524U,	// FMAX_A_W
    536891352U,	// FMAX_D
    536897127U,	// FMAX_W
    536889586U,	// FMIN_A_D
    536895504U,	// FMIN_A_W
    536890258U,	// FMIN_D
    536896039U,	// FMIN_W
    20381U,	// FMOV_D32
    20381U,	// FMOV_D32_MM
    20381U,	// FMOV_D64
    20381U,	// FMOV_D64_MM
    20381U,	// FMOV_D_MMR6
    23880U,	// FMOV_S
    23880U,	// FMOV_S_MM
    23880U,	// FMOV_S_MMR6
    570444079U,	// FMSUB_D
    570449981U,	// FMSUB_W
    536890242U,	// FMUL_D
    536890243U,	// FMUL_D32
    536890243U,	// FMUL_D32_MM
    536890243U,	// FMUL_D64
    536890243U,	// FMUL_D64_MM
    536894951U,	// FMUL_PS64
    536894525U,	// FMUL_S
    536894525U,	// FMUL_S_MM
    570448957U,	// FMUL_S_MMR6
    536896023U,	// FMUL_W
    19073U,	// FNEG_D32
    19073U,	// FNEG_D32_MM
    19073U,	// FNEG_D64
    19073U,	// FNEG_D64_MM
    23532U,	// FNEG_S
    23532U,	// FNEG_S_MM
    23532U,	// FNEG_S_MMR6
    2752567255U,	// FORK
    19407U,	// FRCP_D
    25160U,	// FRCP_W
    20027U,	// FRINT_D
    25850U,	// FRINT_W
    20055U,	// FRSQRT_D
    25878U,	// FRSQRT_W
    536889934U,	// FSAF_D
    536895710U,	// FSAF_W
    536890382U,	// FSEQ_D
    536896149U,	// FSEQ_W
    536889797U,	// FSLE_D
    536895633U,	// FSLE_W
    536890873U,	// FSLT_D
    536896728U,	// FSLT_W
    536889863U,	// FSNE_D
    536895667U,	// FSNE_W
    536890472U,	// FSOR_D
    536896278U,	// FSOR_W
    20046U,	// FSQRT_D
    20047U,	// FSQRT_D32
    20047U,	// FSQRT_D32_MM
    20047U,	// FSQRT_D64
    20047U,	// FSQRT_D64_MM
    23857U,	// FSQRT_S
    23857U,	// FSQRT_S_MM
    25869U,	// FSQRT_W
    536889639U,	// FSUB_D
    536889640U,	// FSUB_D32
    536889640U,	// FSUB_D32_MM
    536889640U,	// FSUB_D64
    536889640U,	// FSUB_D64_MM
    536894927U,	// FSUB_PS64
    536894268U,	// FSUB_S
    536894268U,	// FSUB_S_MM
    570448700U,	// FSUB_S_MMR6
    536895541U,	// FSUB_W
    536890431U,	// FSUEQ_D
    536896166U,	// FSUEQ_W
    536889846U,	// FSULE_D
    536895650U,	// FSULE_W
    536890922U,	// FSULT_D
    536896745U,	// FSULT_W
    536889880U,	// FSUNE_D
    536895684U,	// FSUNE_W
    536890303U,	// FSUN_D
    536896055U,	// FSUN_W
    19821U,	// FTINT_S_D
    25685U,	// FTINT_S_W
    20300U,	// FTINT_U_D
    26115U,	// FTINT_U_W
    536892037U,	// FTQ_H
    536896175U,	// FTQ_W
    19643U,	// FTRUNC_S_D
    25457U,	// FTRUNC_S_W
    20110U,	// FTRUNC_U_D
    25925U,	// FTRUNC_U_W
    546758U,	// GINVI
    546758U,	// GINVI_MMR6
    218127986U,	// GINVT
    218127986U,	// GINVT_MMR6
    536890567U,	// HADD_S_D
    536892116U,	// HADD_S_H
    536896381U,	// HADD_S_W
    536891034U,	// HADD_U_D
    536892404U,	// HADD_U_H
    536896849U,	// HADD_U_W
    536890534U,	// HSUB_S_D
    536892095U,	// HSUB_S_H
    536896348U,	// HSUB_S_W
    536891001U,	// HSUB_U_D
    536892383U,	// HSUB_U_H
    536896816U,	// HSUB_U_W
    645291U,	// HYPCALL
    645291U,	// HYPCALL_MM
    536888837U,	// ILVEV_B
    536891268U,	// ILVEV_D
    536892626U,	// ILVEV_H
    536897093U,	// ILVEV_W
    536888365U,	// ILVL_B
    536890250U,	// ILVL_D
    536891952U,	// ILVL_H
    536896031U,	// ILVL_W
    536888117U,	// ILVOD_B
    536889723U,	// ILVOD_D
    536891754U,	// ILVOD_H
    536895616U,	// ILVOD_W
    536888413U,	// ILVR_B
    536890507U,	// ILVR_D
    536892077U,	// ILVR_H
    536896321U,	// ILVR_W
    536894916U,	// INS
    241714476U,	// INSERT_B
    258494020U,	// INSERT_D
    275272645U,	// INSERT_H
    292054275U,	// INSERT_W
    33578991U,	// INSV
    308822846U,	// INSVE_B
    325601825U,	// INSVE_D
    342380915U,	// INSVE_H
    359162061U,	// INSVE_W
    33578991U,	// INSV_MM
    536894916U,	// INS_MM
    536894916U,	// INS_MMR6
    186317U,	// J
    186356U,	// JAL
    23264U,	// JALR
    547552U,	// JALR16_MM
    23264U,	// JALR64
    547552U,	// JALRC16_MMR6
    17977U,	// JALRC_HB_MMR6
    18516U,	// JALRC_MMR6
    541239U,	// JALRS16_MM
    24100U,	// JALRS_MM
    17994U,	// JALR_HB
    17994U,	// JALR_HB64
    23264U,	// JALR_MM
    187819U,	// JALS_MM
    190126U,	// JALX
    190126U,	// JALX_MM
    186356U,	// JAL_MM
    18395U,	// JIALC
    18395U,	// JIALC64
    18395U,	// JIALC_MMR6
    18384U,	// JIC
    18384U,	// JIC64
    18384U,	// JIC_MMR6
    547548U,	// JR
    541226U,	// JR16_MM
    547548U,	// JR64
    547353U,	// JRADDIUSP
    542799U,	// JRC16_MM
    541104U,	// JRC16_MMR6
    547341U,	// JRCADDIUSP_MMR6
    542275U,	// JR_HB
    542275U,	// JR_HB64
    542275U,	// JR_HB64_R6
    542275U,	// JR_HB_R6
    547548U,	// JR_MM
    186317U,	// J_MM
    7542772U,	// Jal16
    8067060U,	// JalB16
    10524U,	// JrRa16
    10516U,	// JrcRa16
    542799U,	// JrcRx16
    542804U,	// JumpLinkReg16
    50349651U,	// LB
    50349651U,	// LB64
    50352227U,	// LBE
    50352227U,	// LBE_MM
    50348615U,	// LBU16_MM
    3254806196U,	// LBUX
    3254806196U,	// LBUX_MM
    50355845U,	// LBU_MMR6
    50349651U,	// LB_MM
    50349651U,	// LB_MMR6
    50355845U,	// LBu
    50355845U,	// LBu64
    50352363U,	// LBuE
    50352363U,	// LBuE_MM
    50355845U,	// LBu_MM
    50352186U,	// LD
    50348118U,	// LDC1
    50348118U,	// LDC164
    50348118U,	// LDC1_D64_MMR6
    50348118U,	// LDC1_MM_D32
    50348118U,	// LDC1_MM_D64
    50348334U,	// LDC2
    50348334U,	// LDC2_MMR6
    50348334U,	// LDC2_R6
    50348419U,	// LDC3
    17248U,	// LDI_B
    19089U,	// LDI_D
    20885U,	// LDI_H
    24912U,	// LDI_W
    50354256U,	// LDL
    18462U,	// LDPC
    50354842U,	// LDR
    3254796438U,	// LDXC1
    3254796438U,	// LDXC164
    50348838U,	// LD_B
    50350444U,	// LD_D
    50352475U,	// LD_H
    50356337U,	// LD_W
    134242016U,	// LEA_ADDiu
    134242015U,	// LEA_ADDiu64
    134242016U,	// LEA_ADDiu_MM
    50353427U,	// LH
    50353427U,	// LH64
    50352279U,	// LHE
    50352279U,	// LHE_MM
    50348638U,	// LHU16_MM
    3254806185U,	// LHX
    3254806185U,	// LHX_MM
    50353427U,	// LH_MM
    50355923U,	// LHu
    50355923U,	// LHu64
    50352369U,	// LHuE
    50352369U,	// LHuE_MM
    50355923U,	// LHu_MM
    16878U,	// LI16_MM
    16878U,	// LI16_MMR6
    50354352U,	// LL
    50354352U,	// LL64
    50354352U,	// LL64_R6
    50352190U,	// LLD
    50352190U,	// LLD_R6
    50352302U,	// LLE
    50352302U,	// LLE_MM
    50354352U,	// LL_MM
    50354352U,	// LL_MMR6
    50354352U,	// LL_R6
    536888020U,	// LSA
    3828450004U,	// LSA_MMR6
    536888020U,	// LSA_R6
    201349057U,	// LUI_MMR6
    3254796452U,	// LUXC1
    3254796452U,	// LUXC164
    3254796452U,	// LUXC1_MM
    201349057U,	// LUi
    201349057U,	// LUi64
    201349057U,	// LUi_MM
    50357902U,	// LW
    50348645U,	// LW16_MM
    50357902U,	// LW64
    50348170U,	// LWC1
    50348170U,	// LWC1_MM
    50348386U,	// LWC2
    50348386U,	// LWC2_MMR6
    50348386U,	// LWC2_R6
    50348431U,	// LWC3
    50357902U,	// LWDSP
    50357902U,	// LWDSP_MM
    50352381U,	// LWE
    50352381U,	// LWE_MM
    50357902U,	// LWGP_MM
    50354470U,	// LWL
    50354470U,	// LWL64
    50352312U,	// LWLE
    50352312U,	// LWLE_MM
    50354470U,	// LWL_MM
    66059U,	// LWM16_MM
    66059U,	// LWM16_MMR6
    65799U,	// LWM32_MM
    18499U,	// LWPC
    18499U,	// LWPC_MMR6
    369121850U,	// LWP_MM
    50354976U,	// LWR
    50354976U,	// LWR64
    50352351U,	// LWRE
    50352351U,	// LWRE_MM
    50354976U,	// LWR_MM
    50357902U,	// LWSP_MM
    18492U,	// LWUPC
    50356070U,	// LWU_MM
    3254806202U,	// LWX
    3254796466U,	// LWXC1
    3254796466U,	// LWXC1_MM
    3254804017U,	// LWXS_MM
    3254806202U,	// LWX_MM
    50357902U,	// LW_MM
    50357902U,	// LW_MMR6
    50356070U,	// LWu
    50349651U,	// LbRxRyOffMemX16
    50355845U,	// LbuRxRyOffMemX16
    50353427U,	// LhRxRyOffMemX16
    50355923U,	// LhuRxRyOffMemX16
    1610635144U,	// LiRxImm16
    22398U,	// LiRxImmAlignX16
    22408U,	// LiRxImmX16
    26254U,	// LwRxPcTcp16
    26254U,	// LwRxPcTcpX16
    50357902U,	// LwRxRyOffMemX16
    50357902U,	// LwRxSpImmX16
    20523U,	// MADD
    570444383U,	// MADDF_D
    570444383U,	// MADDF_D_MMR6
    570448851U,	// MADDF_S
    570448851U,	// MADDF_S_MMR6
    570446441U,	// MADDR_Q_H
    570450552U,	// MADDR_Q_W
    24230U,	// MADDU
    536895142U,	// MADDU_DSP
    536895142U,	// MADDU_DSP_MM
    24230U,	// MADDU_MM
    570443251U,	// MADDV_B
    570445682U,	// MADDV_D
    570447040U,	// MADDV_H
    570451507U,	// MADDV_W
    536889690U,	// MADD_D32
    536889690U,	// MADD_D32_MM
    536889690U,	// MADD_D64
    536891435U,	// MADD_DSP
    536891435U,	// MADD_DSP_MM
    20523U,	// MADD_MM
    570446411U,	// MADD_Q_H
    570450522U,	// MADD_Q_W
    536894285U,	// MADD_S
    536894285U,	// MADD_S_MM
    536893555U,	// MAQ_SA_W_PHL
    536893555U,	// MAQ_SA_W_PHL_MM
    536894116U,	// MAQ_SA_W_PHR
    536894116U,	// MAQ_SA_W_PHR_MM
    536893583U,	// MAQ_S_W_PHL
    536893583U,	// MAQ_S_W_PHL_MM
    536894144U,	// MAQ_S_W_PHR
    536894144U,	// MAQ_S_W_PHR_MM
    536889631U,	// MAXA_D
    536889631U,	// MAXA_D_MMR6
    536894258U,	// MAXA_S
    536894258U,	// MAXA_S_MMR6
    536888488U,	// MAXI_S_B
    536890645U,	// MAXI_S_D
    536892194U,	// MAXI_S_H
    536896459U,	// MAXI_S_W
    536888703U,	// MAXI_U_B
    536891112U,	// MAXI_U_D
    536892482U,	// MAXI_U_H
    536896927U,	// MAXI_U_W
    536888069U,	// MAX_A_B
    536889607U,	// MAX_A_D
    536891706U,	// MAX_A_H
    536895525U,	// MAX_A_W
    536891353U,	// MAX_D
    536891353U,	// MAX_D_MMR6
    536894851U,	// MAX_S
    536888576U,	// MAX_S_B
    536890765U,	// MAX_S_D
    536892313U,	// MAX_S_H
    536894851U,	// MAX_S_MMR6
    536896640U,	// MAX_S_W
    536888791U,	// MAX_U_B
    536891232U,	// MAX_U_D
    536892580U,	// MAX_U_H
    536897047U,	// MAX_U_W
    536887298U,	// MFC0
    536887298U,	// MFC0_MMR6
    16489U,	// MFC1
    16489U,	// MFC1_D64
    16489U,	// MFC1_MM
    16489U,	// MFC1_MMR6
    536887617U,	// MFC2
    16705U,	// MFC2_MMR6
    536887305U,	// MFGC0
    536887305U,	// MFGC0_MM
    536887336U,	// MFHC0_MMR6
    16495U,	// MFHC1_D32
    16495U,	// MFHC1_D32_MM
    16495U,	// MFHC1_D64
    16495U,	// MFHC1_D64_MM
    16711U,	// MFHC2_MMR6
    536887312U,	// MFHGC0
    536887312U,	// MFHGC0_MM
    546674U,	// MFHI
    541158U,	// MFHI16_MM
    546674U,	// MFHI64
    22386U,	// MFHI_DSP
    22386U,	// MFHI_DSP_MM
    546674U,	// MFHI_MM
    547206U,	// MFLO
    541209U,	// MFLO16_MM
    547206U,	// MFLO64
    22918U,	// MFLO_DSP
    22918U,	// MFLO_DSP_MM
    547206U,	// MFLO_MM
    536894214U,	// MFTR
    536889616U,	// MINA_D
    536889616U,	// MINA_D_MMR6
    536894250U,	// MINA_S
    536894250U,	// MINA_S_MMR6
    536888468U,	// MINI_S_B
    536890625U,	// MINI_S_D
    536892174U,	// MINI_S_H
    536896439U,	// MINI_S_W
    536888683U,	// MINI_U_B
    536891092U,	// MINI_U_D
    536892462U,	// MINI_U_H
    536896907U,	// MINI_U_W
    536888050U,	// MIN_A_B
    536889587U,	// MIN_A_D
    536891687U,	// MIN_A_H
    536895505U,	// MIN_A_W
    536890259U,	// MIN_D
    536890259U,	// MIN_D_MMR6
    536894532U,	// MIN_S
    536888498U,	// MIN_S_B
    536890655U,	// MIN_S_D
    536892204U,	// MIN_S_H
    536894532U,	// MIN_S_MMR6
    536896479U,	// MIN_S_W
    536888713U,	// MIN_U_B
    536891122U,	// MIN_U_D
    536892492U,	// MIN_U_H
    536896937U,	// MIN_U_W
    536891482U,	// MOD
    536889255U,	// MODSUB
    536889255U,	// MODSUB_MM
    536895150U,	// MODU
    536895150U,	// MODU_MMR6
    536891482U,	// MOD_MMR6
    536888431U,	// MOD_S_B
    536890588U,	// MOD_S_D
    536892137U,	// MOD_S_H
    536896402U,	// MOD_S_W
    536888646U,	// MOD_U_B
    536891055U,	// MOD_U_D
    536892425U,	// MOD_U_H
    536896870U,	// MOD_U_W
    20727U,	// MOVE16_MM
    16848U,	// MOVE16_MMR6
    536893881U,	// MOVEP_MM
    536893881U,	// MOVEP_MMR6
    24434U,	// MOVE_V
    536889976U,	// MOVF_D32
    536889976U,	// MOVF_D32_MM
    536889976U,	// MOVF_D64
    536891667U,	// MOVF_I
    536891667U,	// MOVF_I64
    536891667U,	// MOVF_I_MM
    536894436U,	// MOVF_S
    536894436U,	// MOVF_S_MM
    536890311U,	// MOVN_I64_D64
    536893818U,	// MOVN_I64_I
    536893818U,	// MOVN_I64_I64
    536894568U,	// MOVN_I64_S
    536890311U,	// MOVN_I_D32
    536890311U,	// MOVN_I_D32_MM
    536890311U,	// MOVN_I_D64
    536893818U,	// MOVN_I_I
    536893818U,	// MOVN_I_I64
    536893818U,	// MOVN_I_MM
    536894568U,	// MOVN_I_S
    536894568U,	// MOVN_I_S_MM
    536890983U,	// MOVT_D32
    536890983U,	// MOVT_D32_MM
    536890983U,	// MOVT_D64
    536895097U,	// MOVT_I
    536895097U,	// MOVT_I64
    536895097U,	// MOVT_I_MM
    536894777U,	// MOVT_S
    536894777U,	// MOVT_S_MM
    536891393U,	// MOVZ_I64_D64
    536897287U,	// MOVZ_I64_I
    536897287U,	// MOVZ_I64_I64
    536894878U,	// MOVZ_I64_S
    536891393U,	// MOVZ_I_D32
    536891393U,	// MOVZ_I_D32_MM
    536891393U,	// MOVZ_I_D64
    536897287U,	// MOVZ_I_I
    536897287U,	// MOVZ_I_I64
    536897287U,	// MOVZ_I_MM
    536894878U,	// MOVZ_I_S
    536894878U,	// MOVZ_I_S_MM
    18351U,	// MSUB
    570444374U,	// MSUBF_D
    570444374U,	// MSUBF_D_MMR6
    570448842U,	// MSUBF_S
    570448842U,	// MSUBF_S_MMR6
    570446430U,	// MSUBR_Q_H
    570450541U,	// MSUBR_Q_W
    24209U,	// MSUBU
    536895121U,	// MSUBU_DSP
    536895121U,	// MSUBU_DSP_MM
    24209U,	// MSUBU_MM
    570443242U,	// MSUBV_B
    570445673U,	// MSUBV_D
    570447031U,	// MSUBV_H
    570451498U,	// MSUBV_W
    536889648U,	// MSUB_D32
    536889648U,	// MSUB_D32_MM
    536889648U,	// MSUB_D64
    536889263U,	// MSUB_DSP
    536889263U,	// MSUB_DSP_MM
    18351U,	// MSUB_MM
    570446401U,	// MSUB_Q_H
    570450512U,	// MSUB_Q_W
    536894267U,	// MSUB_S
    536894267U,	// MSUB_S_MM
    2752561207U,	// MTC0
    2752561207U,	// MTC0_MMR6
    17875076U,	// MTC1
    17875076U,	// MTC1_D64
    17875076U,	// MTC1_D64_MM
    17875076U,	// MTC1_MM
    17875076U,	// MTC1_MMR6
    2752561500U,	// MTC2
    17875292U,	// MTC2_MMR6
    2752561185U,	// MTGC0
    2752561185U,	// MTGC0_MM
    2752561199U,	// MTHC0_MMR6
    17924214U,	// MTHC1_D32
    17924214U,	// MTHC1_D32_MM
    17924214U,	// MTHC1_D64
    17924214U,	// MTHC1_D64_MM
    17875278U,	// MTHC2_MMR6
    2752561176U,	// MTHGC0
    2752561176U,	// MTHGC0_MM
    546680U,	// MTHI
    546680U,	// MTHI64
    17880952U,	// MTHI_DSP
    17880952U,	// MTHI_DSP_MM
    546680U,	// MTHI_MM
    17881536U,	// MTHLIP
    17881536U,	// MTHLIP_MM
    547219U,	// MTLO
    547219U,	// MTLO64
    17881491U,	// MTLO_DSP
    17881491U,	// MTLO_DSP_MM
    547219U,	// MTLO_MM
    540739U,	// MTM0
    540864U,	// MTM1
    541038U,	// MTM2
    540745U,	// MTP0
    540870U,	// MTP1
    541044U,	// MTP2
    68213523U,	// MTTR
    536893249U,	// MUH
    536895193U,	// MUHU
    536895193U,	// MUHU_MMR6
    536893249U,	// MUH_MMR6
    536893715U,	// MUL
    536893596U,	// MULEQ_S_W_PHL
    536893596U,	// MULEQ_S_W_PHL_MM
    536894157U,	// MULEQ_S_W_PHR
    536894157U,	// MULEQ_S_W_PHR_MM
    536893473U,	// MULEU_S_PH_QBL
    536893473U,	// MULEU_S_PH_QBL_MM
    536894059U,	// MULEU_S_PH_QBR
    536894059U,	// MULEU_S_PH_QBR_MM
    536893009U,	// MULQ_RS_PH
    536893009U,	// MULQ_RS_PH_MM
    536896659U,	// MULQ_RS_W
    536896659U,	// MULQ_RS_W_MMR2
    536892953U,	// MULQ_S_PH
    536892953U,	// MULQ_S_PH_MMR2
    536896518U,	// MULQ_S_W
    536896518U,	// MULQ_S_W_MMR2
    536894976U,	// MULR_PS64
    536892020U,	// MULR_Q_H
    536896131U,	// MULR_Q_W
    536893155U,	// MULSAQ_S_W_PH
    536893155U,	// MULSAQ_S_W_PH_MM
    536893130U,	// MULSA_W_PH
    536893130U,	// MULSA_W_PH_MMR2
    24157U,	// MULT
    536895313U,	// MULTU_DSP
    536895313U,	// MULTU_DSP_MM
    536895069U,	// MULT_DSP
    536895069U,	// MULT_DSP_MM
    24157U,	// MULT_MM
    24401U,	// MULTu
    24401U,	// MULTu_MM
    536895230U,	// MULU
    536895230U,	// MULU_MMR6
    536888846U,	// MULV_B
    536891285U,	// MULV_D
    536892635U,	// MULV_H
    536897110U,	// MULV_W
    536893715U,	// MUL_MM
    536893715U,	// MUL_MMR6
    536892826U,	// MUL_PH
    536892826U,	// MUL_PH_MMR2
    536891989U,	// MUL_Q_H
    536896100U,	// MUL_Q_W
    536893715U,	// MUL_R6
    536892921U,	// MUL_S_PH
    536892921U,	// MUL_S_PH_MMR2
    546674U,	// Mfhi16
    547206U,	// Mflo16
    20727U,	// Move32R16
    20727U,	// MoveR3216
    17173U,	// NLOC_B
    18753U,	// NLOC_D
    20810U,	// NLOC_H
    24646U,	// NLOC_W
    17181U,	// NLZC_B
    18761U,	// NLZC_D
    20818U,	// NLZC_H
    24654U,	// NLZC_W
    536889698U,	// NMADD_D32
    536889698U,	// NMADD_D32_MM
    536889698U,	// NMADD_D64
    536894284U,	// NMADD_S
    536894284U,	// NMADD_S_MM
    536889656U,	// NMSUB_D32
    536889656U,	// NMSUB_D32_MM
    536889656U,	// NMSUB_D64
    536894266U,	// NMSUB_S
    536894266U,	// NMSUB_S_MM
    536894182U,	// NOR
    536894182U,	// NOR64
    536888254U,	// NORI_B
    536894182U,	// NOR_MM
    536894182U,	// NOR_MMR6
    536895362U,	// NOR_V
    16960U,	// NOT16_MM
    16960U,	// NOT16_MMR6
    20761U,	// NegRxRy16
    24173U,	// NotRxRy16
    536894183U,	// OR
    20021809U,	// OR16_MM
    20021809U,	// OR16_MMR6
    536894183U,	// OR64
    536888255U,	// ORI_B
    536893348U,	// ORI_MMR6
    536894183U,	// OR_MM
    536894183U,	// OR_MMR6
    536895363U,	// OR_V
    536893348U,	// ORi
    536893348U,	// ORi64
    536893348U,	// ORi_MM
    33577703U,	// OrRxRxRy16
    536892815U,	// PACKRL_PH
    536892815U,	// PACKRL_PH_MM
    10542U,	// PAUSE
    10542U,	// PAUSE_MM
    10542U,	// PAUSE_MMR6
    536888828U,	// PCKEV_B
    536891259U,	// PCKEV_D
    536892617U,	// PCKEV_H
    536897084U,	// PCKEV_W
    536888108U,	// PCKOD_B
    536889714U,	// PCKOD_D
    536891745U,	// PCKOD_H
    536895607U,	// PCKOD_W
    17700U,	// PCNT_B
    20019U,	// PCNT_D
    21437U,	// PCNT_H
    25842U,	// PCNT_W
    536892779U,	// PICK_PH
    536892779U,	// PICK_PH_MM
    536888987U,	// PICK_QB
    536888987U,	// PICK_QB_MM
    536894943U,	// PLL_PS64
    536894985U,	// PLU_PS64
    22990U,	// POP
    22592U,	// PRECEQU_PH_QBL
    17046U,	// PRECEQU_PH_QBLA
    17046U,	// PRECEQU_PH_QBLA_MM
    22592U,	// PRECEQU_PH_QBL_MM
    23178U,	// PRECEQU_PH_QBR
    17084U,	// PRECEQU_PH_QBRA
    17084U,	// PRECEQU_PH_QBRA_MM
    23178U,	// PRECEQU_PH_QBR_MM
    22657U,	// PRECEQ_W_PHL
    22657U,	// PRECEQ_W_PHL_MM
    23218U,	// PRECEQ_W_PHR
    23218U,	// PRECEQ_W_PHR_MM
    22577U,	// PRECEU_PH_QBL
    17030U,	// PRECEU_PH_QBLA
    17030U,	// PRECEU_PH_QBLA_MM
    22577U,	// PRECEU_PH_QBL_MM
    23163U,	// PRECEU_PH_QBR
    17068U,	// PRECEU_PH_QBRA
    17068U,	// PRECEU_PH_QBRA_MM
    23163U,	// PRECEU_PH_QBR_MM
    536892731U,	// PRECRQU_S_QB_PH
    536892731U,	// PRECRQU_S_QB_PH_MM
    536895750U,	// PRECRQ_PH_W
    536895750U,	// PRECRQ_PH_W_MM
    536892704U,	// PRECRQ_QB_PH
    536892704U,	// PRECRQ_QB_PH_MM
    536895781U,	// PRECRQ_RS_PH_W
    536895781U,	// PRECRQ_RS_PH_W_MM
    536892718U,	// PRECR_QB_PH
    536892718U,	// PRECR_QB_PH_MMR2
    536895734U,	// PRECR_SRA_PH_W
    536895734U,	// PRECR_SRA_PH_W_MMR2
    536895763U,	// PRECR_SRA_R_PH_W
    536895763U,	// PRECR_SRA_R_PH_W_MMR2
    5394701U,	// PREF
    5394554U,	// PREFE
    5394554U,	// PREFE_MM
    389179042U,	// PREFX_MM
    5394701U,	// PREF_MM
    5394701U,	// PREF_MMR6
    5394701U,	// PREF_R6
    536891464U,	// PREPEND
    536891464U,	// PREPEND_MMR2
    536894959U,	// PUL_PS64
    536894993U,	// PUU_PS64
    18327U,	// RADDU_W_QB
    18327U,	// RADDU_W_QB_MM
    184572415U,	// RDDSP
    402676223U,	// RDDSP_MM
    536894233U,	// RDHWR
    536894233U,	// RDHWR64
    536894233U,	// RDHWR_MM
    536894233U,	// RDHWR_MMR6
    23286U,	// RDPGPR_MMR6
    19415U,	// RECIP_D32
    19415U,	// RECIP_D32_MM
    19415U,	// RECIP_D64
    19415U,	// RECIP_D64_MM
    23664U,	// RECIP_S
    23664U,	// RECIP_S_MM
    22158U,	// REPLV_PH
    22158U,	// REPLV_PH_MM
    18307U,	// REPLV_QB
    18307U,	// REPLV_QB_MM
    21885U,	// REPL_PH
    21885U,	// REPL_PH_MM
    419448493U,	// REPL_QB
    419448493U,	// REPL_QB_MM
    20028U,	// RINT_D
    20028U,	// RINT_D_MMR6
    23848U,	// RINT_S
    23848U,	// RINT_S_MMR6
    536894221U,	// ROTR
    536895464U,	// ROTRV
    536895464U,	// ROTRV_MM
    536894221U,	// ROTR_MM
    19224U,	// ROUND_L_D64
    19224U,	// ROUND_L_D_MMR6
    23556U,	// ROUND_L_S
    23556U,	// ROUND_L_S_MMR6
    20399U,	// ROUND_W_D32
    20399U,	// ROUND_W_D64
    20399U,	// ROUND_W_D_MMR6
    20399U,	// ROUND_W_MM
    23898U,	// ROUND_W_S
    23898U,	// ROUND_W_S_MM
    23898U,	// ROUND_W_S_MMR6
    20056U,	// RSQRT_D32
    20056U,	// RSQRT_D32_MM
    20056U,	// RSQRT_D64
    20056U,	// RSQRT_D64_MM
    23856U,	// RSQRT_S
    23856U,	// RSQRT_S_MM
    0U,	// Restore16
    0U,	// RestoreX16
    8405633U,	// SAA
    8409105U,	// SAAD
    536888537U,	// SAT_S_B
    536890704U,	// SAT_S_D
    536892263U,	// SAT_S_H
    536896568U,	// SAT_S_W
    536888764U,	// SAT_U_B
    536891183U,	// SAT_U_D
    536892553U,	// SAT_U_H
    536896998U,	// SAT_U_W
    50349987U,	// SB
    50348452U,	// SB16_MM
    50348452U,	// SB16_MMR6
    50349987U,	// SB64
    50352232U,	// SBE
    50352232U,	// SBE_MM
    50349987U,	// SB_MM
    50349987U,	// SB_MMR6
    8964190U,	// SC
    8964190U,	// SC64
    8964190U,	// SC64_R6
    8966176U,	// SCD
    8966176U,	// SCD_R6
    8966253U,	// SCE
    8966253U,	// SCE_MM
    8964190U,	// SC_MM
    8964190U,	// SC_MMR6
    8964190U,	// SC_R6
    50352223U,	// SD
    219562U,	// SDBBP
    131617U,	// SDBBP16_MM
    131617U,	// SDBBP16_MMR6
    645546U,	// SDBBP_MM
    219562U,	// SDBBP_MMR6
    219562U,	// SDBBP_R6
    50348124U,	// SDC1
    50348124U,	// SDC164
    50348124U,	// SDC1_D64_MMR6
    50348124U,	// SDC1_MM_D32
    50348124U,	// SDC1_MM_D64
    50348340U,	// SDC2
    50348340U,	// SDC2_MMR6
    50348340U,	// SDC2_R6
    50348425U,	// SDC3
    26408U,	// SDIV
    26408U,	// SDIV_MM
    50354261U,	// SDL
    50354847U,	// SDR
    3254796445U,	// SDXC1
    3254796445U,	// SDXC164
    17972U,	// SEB
    17972U,	// SEB64
    17972U,	// SEB_MM
    21773U,	// SEH
    21773U,	// SEH64
    21773U,	// SEH_MM
    536897260U,	// SELEQZ
    536897260U,	// SELEQZ64
    536891383U,	// SELEQZ_D
    536891383U,	// SELEQZ_D_MMR6
    536897260U,	// SELEQZ_MMR6
    536894868U,	// SELEQZ_S
    536894868U,	// SELEQZ_S_MMR6
    536897233U,	// SELNEZ
    536897233U,	// SELNEZ64
    536891366U,	// SELNEZ_D
    536891366U,	// SELNEZ_D_MMR6
    536897233U,	// SELNEZ_MMR6
    536894858U,	// SELNEZ_S
    536894858U,	// SELNEZ_S_MMR6
    570444609U,	// SEL_D
    570444609U,	// SEL_D_MMR6
    570448941U,	// SEL_S
    570448941U,	// SEL_S_MMR6
    536894025U,	// SEQ
    536893335U,	// SEQi
    50353980U,	// SH
    50348504U,	// SH16_MM
    50348504U,	// SH16_MMR6
    50353980U,	// SH64
    50352284U,	// SHE
    50352284U,	// SHE_MM
    536888136U,	// SHF_B
    536891773U,	// SHF_H
    536895719U,	// SHF_W
    22924U,	// SHILO
    24527U,	// SHILOV
    24527U,	// SHILOV_MM
    22924U,	// SHILO_MM
    536893060U,	// SHLLV_PH
    536893060U,	// SHLLV_PH_MM
    536889209U,	// SHLLV_QB
    536889209U,	// SHLLV_QB_MM
    536892997U,	// SHLLV_S_PH
    536892997U,	// SHLLV_S_PH_MM
    536896629U,	// SHLLV_S_W
    536896629U,	// SHLLV_S_W_MM
    536892788U,	// SHLL_PH
    536892788U,	// SHLL_PH_MM
    536888996U,	// SHLL_QB
    536888996U,	// SHLL_QB_MM
    536892910U,	// SHLL_S_PH
    536892910U,	// SHLL_S_PH_MM
    536896469U,	// SHLL_S_W
    536896469U,	// SHLL_S_W_MM
    536893050U,	// SHRAV_PH
    536893050U,	// SHRAV_PH_MM
    536889199U,	// SHRAV_QB
    536889199U,	// SHRAV_QB_MMR2
    536892898U,	// SHRAV_R_PH
    536892898U,	// SHRAV_R_PH_MM
    536889097U,	// SHRAV_R_QB
    536889097U,	// SHRAV_R_QB_MMR2
    536896224U,	// SHRAV_R_W
    536896224U,	// SHRAV_R_W_MM
    536892695U,	// SHRA_PH
    536892695U,	// SHRA_PH_MM
    536888919U,	// SHRA_QB
    536888919U,	// SHRA_QB_MMR2
    536892863U,	// SHRA_R_PH
    536892863U,	// SHRA_R_PH_MM
    536889062U,	// SHRA_R_QB
    536889062U,	// SHRA_R_QB_MMR2
    536896182U,	// SHRA_R_W
    536896182U,	// SHRA_R_W_MM
    536893080U,	// SHRLV_PH
    536893080U,	// SHRLV_PH_MMR2
    536889229U,	// SHRLV_QB
    536889229U,	// SHRLV_QB_MM
    536892806U,	// SHRL_PH
    536892806U,	// SHRL_PH_MMR2
    536889014U,	// SHRL_QB
    536889014U,	// SHRL_QB_MM
    50353980U,	// SH_MM
    50353980U,	// SH_MMR6
    233633U,	// SIGRIE
    233633U,	// SIGRIE_MMR6
    1107313503U,	// SLDI_B
    1107315344U,	// SLDI_D
    1107317140U,	// SLDI_H
    1107321167U,	// SLDI_W
    1107313445U,	// SLD_B
    1107315051U,	// SLD_D
    1107317082U,	// SLD_H
    1107320944U,	// SLD_W
    536893648U,	// SLL
    536887805U,	// SLL16_MM
    536887805U,	// SLL16_MMR6
    536893648U,	// SLL64_32
    536893648U,	// SLL64_64
    536888193U,	// SLLI_B
    536890017U,	// SLLI_D
    536891813U,	// SLLI_H
    536895840U,	// SLLI_W
    536895426U,	// SLLV
    536895426U,	// SLLV_MM
    536888342U,	// SLL_B
    536890201U,	// SLL_D
    536891929U,	// SLL_H
    536893648U,	// SLL_MM
    536893648U,	// SLL_MMR6
    536895982U,	// SLL_W
    536895058U,	// SLT
    536895058U,	// SLT64
    536895058U,	// SLT_MM
    536893359U,	// SLTi
    536893359U,	// SLTi64
    536893359U,	// SLTi_MM
    536895214U,	// SLTiu
    536895214U,	// SLTiu64
    536895214U,	// SLTiu_MM
    536895300U,	// SLTu
    536895300U,	// SLTu64
    536895300U,	// SLTu_MM
    536891593U,	// SNE
    536893280U,	// SNEi
    1073759192U,	// SPLATI_B
    1073761000U,	// SPLATI_D
    1073762796U,	// SPLATI_H
    1073766823U,	// SPLATI_W
    1073759507U,	// SPLAT_B
    1073761713U,	// SPLAT_D
    1073763244U,	// SPLAT_H
    1073767615U,	// SPLAT_W
    536888014U,	// SRA
    536888151U,	// SRAI_B
    536889992U,	// SRAI_D
    536891788U,	// SRAI_H
    536895815U,	// SRAI_W
    536888227U,	// SRARI_B
    536890051U,	// SRARI_D
    536891847U,	// SRARI_H
    536895874U,	// SRARI_W
    536888380U,	// SRAR_B
    536890440U,	// SRAR_D
    536892044U,	// SRAR_H
    536896246U,	// SRAR_W
    536895405U,	// SRAV
    536895405U,	// SRAV_MM
    536888078U,	// SRA_B
    536889624U,	// SRA_D
    536891715U,	// SRA_H
    536888014U,	// SRA_MM
    536895534U,	// SRA_W
    536893676U,	// SRL
    536887812U,	// SRL16_MM
    536887812U,	// SRL16_MMR6
    536888201U,	// SRLI_B
    536890025U,	// SRLI_D
    536891821U,	// SRLI_H
    536895848U,	// SRLI_W
    536888245U,	// SRLRI_B
    536890069U,	// SRLRI_D
    536891865U,	// SRLRI_H
    536895892U,	// SRLRI_W
    536888396U,	// SRLR_B
    536890456U,	// SRLR_D
    536892060U,	// SRLR_H
    536896262U,	// SRLR_W
    536895433U,	// SRLV
    536895433U,	// SRLV_MM
    536888349U,	// SRL_B
    536890226U,	// SRL_D
    536891936U,	// SRL_H
    536893676U,	// SRL_MM
    536896007U,	// SRL_W
    10607U,	// SSNOP
    10607U,	// SSNOP_MM
    10607U,	// SSNOP_MMR6
    50349366U,	// ST_B
    50351713U,	// ST_D
    50353103U,	// ST_H
    50357536U,	// ST_W
    536889258U,	// SUB
    536892759U,	// SUBQH_PH
    536892759U,	// SUBQH_PH_MMR2
    536892874U,	// SUBQH_R_PH
    536892874U,	// SUBQH_R_PH_MMR2
    536896192U,	// SUBQH_R_W
    536896192U,	// SUBQH_R_W_MMR2
    536895797U,	// SUBQH_W
    536895797U,	// SUBQH_W_MMR2
    536892834U,	// SUBQ_PH
    536892834U,	// SUBQ_PH_MM
    536892931U,	// SUBQ_S_PH
    536892931U,	// SUBQ_S_PH_MM
    536896498U,	// SUBQ_S_W
    536896498U,	// SUBQ_S_W_MM
    536888752U,	// SUBSUS_U_B
    536891171U,	// SUBSUS_U_D
    536892541U,	// SUBSUS_U_H
    536896986U,	// SUBSUS_U_W
    536888555U,	// SUBSUU_S_B
    536890744U,	// SUBSUU_S_D
    536892281U,	// SUBSUU_S_H
    536896608U,	// SUBSUU_S_W
    536888517U,	// SUBS_S_B
    536890684U,	// SUBS_S_D
    536892243U,	// SUBS_S_H
    536896548U,	// SUBS_S_W
    536888732U,	// SUBS_U_B
    536891151U,	// SUBS_U_D
    536892521U,	// SUBS_U_H
    536896966U,	// SUBS_U_W
    536887886U,	// SUBU16_MM
    536887886U,	// SUBU16_MMR6
    536888967U,	// SUBUH_QB
    536888967U,	// SUBUH_QB_MMR2
    536889073U,	// SUBUH_R_QB
    536889073U,	// SUBUH_R_QB_MMR2
    536895115U,	// SUBU_MMR6
    536893032U,	// SUBU_PH
    536893032U,	// SUBU_PH_MMR2
    536889181U,	// SUBU_QB
    536889181U,	// SUBU_QB_MM
    536892975U,	// SUBU_S_PH
    536892975U,	// SUBU_S_PH_MMR2
    536889120U,	// SUBU_S_QB
    536889120U,	// SUBU_S_QB_MM
    536888299U,	// SUBVI_B
    536890107U,	// SUBVI_D
    536891903U,	// SUBVI_H
    536895930U,	// SUBVI_W
    536888811U,	// SUBV_B
    536891242U,	// SUBV_D
    536892600U,	// SUBV_H
    536897067U,	// SUBV_W
    536889258U,	// SUB_MM
    536889258U,	// SUB_MMR6
    536895115U,	// SUBu
    536895115U,	// SUBu_MM
    3254796459U,	// SUXC1
    3254796459U,	// SUXC164
    3254796459U,	// SUXC1_MM
    50357918U,	// SW
    50348651U,	// SW16_MM
    50348651U,	// SW16_MMR6
    50357918U,	// SW64
    50348176U,	// SWC1
    50348176U,	// SWC1_MM
    50348392U,	// SWC2
    50348392U,	// SWC2_MMR6
    50348392U,	// SWC2_R6
    50348437U,	// SWC3
    50357918U,	// SWDSP
    50357918U,	// SWDSP_MM
    50352386U,	// SWE
    50352386U,	// SWE_MM
    50354475U,	// SWL
    50354475U,	// SWL64
    50352318U,	// SWLE
    50352318U,	// SWLE_MM
    50354475U,	// SWL_MM
    66066U,	// SWM16_MM
    66066U,	// SWM16_MMR6
    65806U,	// SWM32_MM
    369121855U,	// SWP_MM
    50354981U,	// SWR
    50354981U,	// SWR64
    50352357U,	// SWRE
    50352357U,	// SWRE_MM
    50354981U,	// SWR_MM
    50354724U,	// SWSP_MM
    50357918U,	// SWSP_MMR6
    3254796473U,	// SWXC1
    3254796473U,	// SWXC1_MM
    50357918U,	// SW_MM
    50357918U,	// SW_MMR6
    255866U,	// SYNC
    268102U,	// SYNCI
    268102U,	// SYNCI_MM
    268102U,	// SYNCI_MMR6
    255866U,	// SYNC_MM
    247832U,	// SYNC_MMR6
    219316U,	// SYSCALL
    645300U,	// SYSCALL_MM
    0U,	// Save16
    0U,	// SaveX16
    50349987U,	// SbRxRyOffMemX16
    550669U,	// SebRx16
    550675U,	// SehRx16
    50353980U,	// ShRxRyOffMemX16
    536893648U,	// SllX16
    33578946U,	// SllvRxRy16
    24146U,	// SltRxRy16
    1610635183U,	// SltiRxImm16
    22447U,	// SltiRxImmX16
    1610637038U,	// SltiuRxImm16
    24302U,	// SltiuRxImmX16
    24388U,	// SltuRxRy16
    536888014U,	// SraX16
    33578925U,	// SravRxRy16
    536893676U,	// SrlX16
    33578953U,	// SrlvRxRy16
    536895115U,	// SubuRxRyRz16
    50357918U,	// SwRxRyOffMemX16
    50357918U,	// SwRxSpImmX16
    536894030U,	// TEQ
    22429U,	// TEQI
    22429U,	// TEQI_MM
    536894030U,	// TEQ_MM
    536891531U,	// TGE
    22362U,	// TGEI
    24295U,	// TGEIU
    24295U,	// TGEIU_MM
    22362U,	// TGEI_MM
    536895168U,	// TGEU
    536895168U,	// TGEU_MM
    536891531U,	// TGE_MM
    10655U,	// TLBGINV
    10556U,	// TLBGINVF
    10556U,	// TLBGINVF_MM
    10655U,	// TLBGINV_MM
    10601U,	// TLBGP
    10601U,	// TLBGP_MM
    10618U,	// TLBGR
    10618U,	// TLBGR_MM
    10571U,	// TLBGWI
    10571U,	// TLBGWI_MM
    10630U,	// TLBGWR
    10630U,	// TLBGWR_MM
    10648U,	// TLBINV
    10548U,	// TLBINVF
    10548U,	// TLBINVF_MMR6
    10648U,	// TLBINV_MMR6
    10596U,	// TLBP
    10596U,	// TLBP_MM
    10613U,	// TLBR
    10613U,	// TLBR_MM
    10565U,	// TLBWI
    10565U,	// TLBWI_MM
    10624U,	// TLBWR
    10624U,	// TLBWR_MM
    536895063U,	// TLT
    22453U,	// TLTI
    24309U,	// TLTIU_MM
    22453U,	// TLTI_MM
    536895306U,	// TLTU
    536895306U,	// TLTU_MM
    536895063U,	// TLT_MM
    536891598U,	// TNE
    22374U,	// TNEI
    22374U,	// TNEI_MM
    536891598U,	// TNE_MM
    19213U,	// TRUNC_L_D64
    19213U,	// TRUNC_L_D_MMR6
    23545U,	// TRUNC_L_S
    23545U,	// TRUNC_L_S_MMR6
    20388U,	// TRUNC_W_D32
    20388U,	// TRUNC_W_D64
    20388U,	// TRUNC_W_D_MMR6
    20388U,	// TRUNC_W_MM
    23887U,	// TRUNC_W_S
    23887U,	// TRUNC_W_S_MM
    23887U,	// TRUNC_W_S_MMR6
    24309U,	// TTLTIU
    26394U,	// UDIV
    26394U,	// UDIV_MM
    536895228U,	// V3MULU
    536887357U,	// VMM0
    536895243U,	// VMULU
    570442567U,	// VSHF_B
    570444392U,	// VSHF_D
    570446204U,	// VSHF_H
    570450150U,	// VSHF_W
    10643U,	// WAIT
    646727U,	// WAIT_MM
    646727U,	// WAIT_MMR6
    184572422U,	// WRDSP
    402676230U,	// WRDSP_MM
    23294U,	// WRPGPR_MMR6
    21758U,	// WSBH
    21758U,	// WSBH_MM
    21758U,	// WSBH_MMR6
    536894193U,	// XOR
    20021808U,	// XOR16_MM
    20021808U,	// XOR16_MMR6
    536894193U,	// XOR64
    536888262U,	// XORI_B
    536893347U,	// XORI_MMR6
    536894193U,	// XOR_MM
    536894193U,	// XOR_MMR6
    536895369U,	// XOR_V
    536893347U,	// XORi
    536893347U,	// XORi64
    536893347U,	// XORi_MM
    33577713U,	// XorRxRxRy16
    20535U,	// YIELD
  };

  static const uint16_t OpInfo1[] = {
    0U,	// PHI
    0U,	// INLINEASM
    0U,	// INLINEASM_BR
    0U,	// CFI_INSTRUCTION
    0U,	// EH_LABEL
    0U,	// GC_LABEL
    0U,	// ANNOTATION_LABEL
    0U,	// KILL
    0U,	// EXTRACT_SUBREG
    0U,	// INSERT_SUBREG
    0U,	// IMPLICIT_DEF
    0U,	// SUBREG_TO_REG
    0U,	// COPY_TO_REGCLASS
    0U,	// DBG_VALUE
    0U,	// DBG_VALUE_LIST
    0U,	// DBG_INSTR_REF
    0U,	// DBG_PHI
    0U,	// DBG_LABEL
    0U,	// REG_SEQUENCE
    0U,	// COPY
    0U,	// BUNDLE
    0U,	// LIFETIME_START
    0U,	// LIFETIME_END
    0U,	// PSEUDO_PROBE
    0U,	// ARITH_FENCE
    0U,	// STACKMAP
    0U,	// FENTRY_CALL
    0U,	// PATCHPOINT
    0U,	// LOAD_STACK_GUARD
    0U,	// PREALLOCATED_SETUP
    0U,	// PREALLOCATED_ARG
    0U,	// STATEPOINT
    0U,	// LOCAL_ESCAPE
    0U,	// FAULTING_OP
    0U,	// PATCHABLE_OP
    0U,	// PATCHABLE_FUNCTION_ENTER
    0U,	// PATCHABLE_RET
    0U,	// PATCHABLE_FUNCTION_EXIT
    0U,	// PATCHABLE_TAIL_CALL
    0U,	// PATCHABLE_EVENT_CALL
    0U,	// PATCHABLE_TYPED_EVENT_CALL
    0U,	// ICALL_BRANCH_FUNNEL
    0U,	// MEMBARRIER
    0U,	// G_ASSERT_SEXT
    0U,	// G_ASSERT_ZEXT
    0U,	// G_ASSERT_ALIGN
    0U,	// G_ADD
    0U,	// G_SUB
    0U,	// G_MUL
    0U,	// G_SDIV
    0U,	// G_UDIV
    0U,	// G_SREM
    0U,	// G_UREM
    0U,	// G_SDIVREM
    0U,	// G_UDIVREM
    0U,	// G_AND
    0U,	// G_OR
    0U,	// G_XOR
    0U,	// G_IMPLICIT_DEF
    0U,	// G_PHI
    0U,	// G_FRAME_INDEX
    0U,	// G_GLOBAL_VALUE
    0U,	// G_EXTRACT
    0U,	// G_UNMERGE_VALUES
    0U,	// G_INSERT
    0U,	// G_MERGE_VALUES
    0U,	// G_BUILD_VECTOR
    0U,	// G_BUILD_VECTOR_TRUNC
    0U,	// G_CONCAT_VECTORS
    0U,	// G_PTRTOINT
    0U,	// G_INTTOPTR
    0U,	// G_BITCAST
    0U,	// G_FREEZE
    0U,	// G_INTRINSIC_FPTRUNC_ROUND
    0U,	// G_INTRINSIC_TRUNC
    0U,	// G_INTRINSIC_ROUND
    0U,	// G_INTRINSIC_LRINT
    0U,	// G_INTRINSIC_ROUNDEVEN
    0U,	// G_READCYCLECOUNTER
    0U,	// G_LOAD
    0U,	// G_SEXTLOAD
    0U,	// G_ZEXTLOAD
    0U,	// G_INDEXED_LOAD
    0U,	// G_INDEXED_SEXTLOAD
    0U,	// G_INDEXED_ZEXTLOAD
    0U,	// G_STORE
    0U,	// G_INDEXED_STORE
    0U,	// G_ATOMIC_CMPXCHG_WITH_SUCCESS
    0U,	// G_ATOMIC_CMPXCHG
    0U,	// G_ATOMICRMW_XCHG
    0U,	// G_ATOMICRMW_ADD
    0U,	// G_ATOMICRMW_SUB
    0U,	// G_ATOMICRMW_AND
    0U,	// G_ATOMICRMW_NAND
    0U,	// G_ATOMICRMW_OR
    0U,	// G_ATOMICRMW_XOR
    0U,	// G_ATOMICRMW_MAX
    0U,	// G_ATOMICRMW_MIN
    0U,	// G_ATOMICRMW_UMAX
    0U,	// G_ATOMICRMW_UMIN
    0U,	// G_ATOMICRMW_FADD
    0U,	// G_ATOMICRMW_FSUB
    0U,	// G_ATOMICRMW_FMAX
    0U,	// G_ATOMICRMW_FMIN
    0U,	// G_ATOMICRMW_UINC_WRAP
    0U,	// G_ATOMICRMW_UDEC_WRAP
    0U,	// G_FENCE
    0U,	// G_BRCOND
    0U,	// G_BRINDIRECT
    0U,	// G_INVOKE_REGION_START
    0U,	// G_INTRINSIC
    0U,	// G_INTRINSIC_W_SIDE_EFFECTS
    0U,	// G_ANYEXT
    0U,	// G_TRUNC
    0U,	// G_CONSTANT
    0U,	// G_FCONSTANT
    0U,	// G_VASTART
    0U,	// G_VAARG
    0U,	// G_SEXT
    0U,	// G_SEXT_INREG
    0U,	// G_ZEXT
    0U,	// G_SHL
    0U,	// G_LSHR
    0U,	// G_ASHR
    0U,	// G_FSHL
    0U,	// G_FSHR
    0U,	// G_ROTR
    0U,	// G_ROTL
    0U,	// G_ICMP
    0U,	// G_FCMP
    0U,	// G_SELECT
    0U,	// G_UADDO
    0U,	// G_UADDE
    0U,	// G_USUBO
    0U,	// G_USUBE
    0U,	// G_SADDO
    0U,	// G_SADDE
    0U,	// G_SSUBO
    0U,	// G_SSUBE
    0U,	// G_UMULO
    0U,	// G_SMULO
    0U,	// G_UMULH
    0U,	// G_SMULH
    0U,	// G_UADDSAT
    0U,	// G_SADDSAT
    0U,	// G_USUBSAT
    0U,	// G_SSUBSAT
    0U,	// G_USHLSAT
    0U,	// G_SSHLSAT
    0U,	// G_SMULFIX
    0U,	// G_UMULFIX
    0U,	// G_SMULFIXSAT
    0U,	// G_UMULFIXSAT
    0U,	// G_SDIVFIX
    0U,	// G_UDIVFIX
    0U,	// G_SDIVFIXSAT
    0U,	// G_UDIVFIXSAT
    0U,	// G_FADD
    0U,	// G_FSUB
    0U,	// G_FMUL
    0U,	// G_FMA
    0U,	// G_FMAD
    0U,	// G_FDIV
    0U,	// G_FREM
    0U,	// G_FPOW
    0U,	// G_FPOWI
    0U,	// G_FEXP
    0U,	// G_FEXP2
    0U,	// G_FLOG
    0U,	// G_FLOG2
    0U,	// G_FLOG10
    0U,	// G_FNEG
    0U,	// G_FPEXT
    0U,	// G_FPTRUNC
    0U,	// G_FPTOSI
    0U,	// G_FPTOUI
    0U,	// G_SITOFP
    0U,	// G_UITOFP
    0U,	// G_FABS
    0U,	// G_FCOPYSIGN
    0U,	// G_IS_FPCLASS
    0U,	// G_FCANONICALIZE
    0U,	// G_FMINNUM
    0U,	// G_FMAXNUM
    0U,	// G_FMINNUM_IEEE
    0U,	// G_FMAXNUM_IEEE
    0U,	// G_FMINIMUM
    0U,	// G_FMAXIMUM
    0U,	// G_PTR_ADD
    0U,	// G_PTRMASK
    0U,	// G_SMIN
    0U,	// G_SMAX
    0U,	// G_UMIN
    0U,	// G_UMAX
    0U,	// G_ABS
    0U,	// G_LROUND
    0U,	// G_LLROUND
    0U,	// G_BR
    0U,	// G_BRJT
    0U,	// G_INSERT_VECTOR_ELT
    0U,	// G_EXTRACT_VECTOR_ELT
    0U,	// G_SHUFFLE_VECTOR
    0U,	// G_CTTZ
    0U,	// G_CTTZ_ZERO_UNDEF
    0U,	// G_CTLZ
    0U,	// G_CTLZ_ZERO_UNDEF
    0U,	// G_CTPOP
    0U,	// G_BSWAP
    0U,	// G_BITREVERSE
    0U,	// G_FCEIL
    0U,	// G_FCOS
    0U,	// G_FSIN
    0U,	// G_FSQRT
    0U,	// G_FFLOOR
    0U,	// G_FRINT
    0U,	// G_FNEARBYINT
    0U,	// G_ADDRSPACE_CAST
    0U,	// G_BLOCK_ADDR
    0U,	// G_JUMP_TABLE
    0U,	// G_DYN_STACKALLOC
    0U,	// G_STRICT_FADD
    0U,	// G_STRICT_FSUB
    0U,	// G_STRICT_FMUL
    0U,	// G_STRICT_FDIV
    0U,	// G_STRICT_FREM
    0U,	// G_STRICT_FMA
    0U,	// G_STRICT_FSQRT
    0U,	// G_READ_REGISTER
    0U,	// G_WRITE_REGISTER
    0U,	// G_MEMCPY
    0U,	// G_MEMCPY_INLINE
    0U,	// G_MEMMOVE
    0U,	// G_MEMSET
    0U,	// G_BZERO
    0U,	// G_VECREDUCE_SEQ_FADD
    0U,	// G_VECREDUCE_SEQ_FMUL
    0U,	// G_VECREDUCE_FADD
    0U,	// G_VECREDUCE_FMUL
    0U,	// G_VECREDUCE_FMAX
    0U,	// G_VECREDUCE_FMIN
    0U,	// G_VECREDUCE_ADD
    0U,	// G_VECREDUCE_MUL
    0U,	// G_VECREDUCE_AND
    0U,	// G_VECREDUCE_OR
    0U,	// G_VECREDUCE_XOR
    0U,	// G_VECREDUCE_SMAX
    0U,	// G_VECREDUCE_SMIN
    0U,	// G_VECREDUCE_UMAX
    0U,	// G_VECREDUCE_UMIN
    0U,	// G_SBFX
    0U,	// G_UBFX
    0U,	// ABSMacro
    0U,	// ADJCALLSTACKDOWN
    0U,	// ADJCALLSTACKUP
    0U,	// AND_V_D_PSEUDO
    0U,	// AND_V_H_PSEUDO
    0U,	// AND_V_W_PSEUDO
    0U,	// ATOMIC_CMP_SWAP_I16
    0U,	// ATOMIC_CMP_SWAP_I16_POSTRA
    0U,	// ATOMIC_CMP_SWAP_I32
    0U,	// ATOMIC_CMP_SWAP_I32_POSTRA
    0U,	// ATOMIC_CMP_SWAP_I64
    0U,	// ATOMIC_CMP_SWAP_I64_POSTRA
    0U,	// ATOMIC_CMP_SWAP_I8
    0U,	// ATOMIC_CMP_SWAP_I8_POSTRA
    0U,	// ATOMIC_LOAD_ADD_I16
    0U,	// ATOMIC_LOAD_ADD_I16_POSTRA
    0U,	// ATOMIC_LOAD_ADD_I32
    0U,	// ATOMIC_LOAD_ADD_I32_POSTRA
    0U,	// ATOMIC_LOAD_ADD_I64
    0U,	// ATOMIC_LOAD_ADD_I64_POSTRA
    0U,	// ATOMIC_LOAD_ADD_I8
    0U,	// ATOMIC_LOAD_ADD_I8_POSTRA
    0U,	// ATOMIC_LOAD_AND_I16
    0U,	// ATOMIC_LOAD_AND_I16_POSTRA
    0U,	// ATOMIC_LOAD_AND_I32
    0U,	// ATOMIC_LOAD_AND_I32_POSTRA
    0U,	// ATOMIC_LOAD_AND_I64
    0U,	// ATOMIC_LOAD_AND_I64_POSTRA
    0U,	// ATOMIC_LOAD_AND_I8
    0U,	// ATOMIC_LOAD_AND_I8_POSTRA
    0U,	// ATOMIC_LOAD_MAX_I16
    0U,	// ATOMIC_LOAD_MAX_I16_POSTRA
    0U,	// ATOMIC_LOAD_MAX_I32
    0U,	// ATOMIC_LOAD_MAX_I32_POSTRA
    0U,	// ATOMIC_LOAD_MAX_I64
    0U,	// ATOMIC_LOAD_MAX_I64_POSTRA
    0U,	// ATOMIC_LOAD_MAX_I8
    0U,	// ATOMIC_LOAD_MAX_I8_POSTRA
    0U,	// ATOMIC_LOAD_MIN_I16
    0U,	// ATOMIC_LOAD_MIN_I16_POSTRA
    0U,	// ATOMIC_LOAD_MIN_I32
    0U,	// ATOMIC_LOAD_MIN_I32_POSTRA
    0U,	// ATOMIC_LOAD_MIN_I64
    0U,	// ATOMIC_LOAD_MIN_I64_POSTRA
    0U,	// ATOMIC_LOAD_MIN_I8
    0U,	// ATOMIC_LOAD_MIN_I8_POSTRA
    0U,	// ATOMIC_LOAD_NAND_I16
    0U,	// ATOMIC_LOAD_NAND_I16_POSTRA
    0U,	// ATOMIC_LOAD_NAND_I32
    0U,	// ATOMIC_LOAD_NAND_I32_POSTRA
    0U,	// ATOMIC_LOAD_NAND_I64
    0U,	// ATOMIC_LOAD_NAND_I64_POSTRA
    0U,	// ATOMIC_LOAD_NAND_I8
    0U,	// ATOMIC_LOAD_NAND_I8_POSTRA
    0U,	// ATOMIC_LOAD_OR_I16
    0U,	// ATOMIC_LOAD_OR_I16_POSTRA
    0U,	// ATOMIC_LOAD_OR_I32
    0U,	// ATOMIC_LOAD_OR_I32_POSTRA
    0U,	// ATOMIC_LOAD_OR_I64
    0U,	// ATOMIC_LOAD_OR_I64_POSTRA
    0U,	// ATOMIC_LOAD_OR_I8
    0U,	// ATOMIC_LOAD_OR_I8_POSTRA
    0U,	// ATOMIC_LOAD_SUB_I16
    0U,	// ATOMIC_LOAD_SUB_I16_POSTRA
    0U,	// ATOMIC_LOAD_SUB_I32
    0U,	// ATOMIC_LOAD_SUB_I32_POSTRA
    0U,	// ATOMIC_LOAD_SUB_I64
    0U,	// ATOMIC_LOAD_SUB_I64_POSTRA
    0U,	// ATOMIC_LOAD_SUB_I8
    0U,	// ATOMIC_LOAD_SUB_I8_POSTRA
    0U,	// ATOMIC_LOAD_UMAX_I16
    0U,	// ATOMIC_LOAD_UMAX_I16_POSTRA
    0U,	// ATOMIC_LOAD_UMAX_I32
    0U,	// ATOMIC_LOAD_UMAX_I32_POSTRA
    0U,	// ATOMIC_LOAD_UMAX_I64
    0U,	// ATOMIC_LOAD_UMAX_I64_POSTRA
    0U,	// ATOMIC_LOAD_UMAX_I8
    0U,	// ATOMIC_LOAD_UMAX_I8_POSTRA
    0U,	// ATOMIC_LOAD_UMIN_I16
    0U,	// ATOMIC_LOAD_UMIN_I16_POSTRA
    0U,	// ATOMIC_LOAD_UMIN_I32
    0U,	// ATOMIC_LOAD_UMIN_I32_POSTRA
    0U,	// ATOMIC_LOAD_UMIN_I64
    0U,	// ATOMIC_LOAD_UMIN_I64_POSTRA
    0U,	// ATOMIC_LOAD_UMIN_I8
    0U,	// ATOMIC_LOAD_UMIN_I8_POSTRA
    0U,	// ATOMIC_LOAD_XOR_I16
    0U,	// ATOMIC_LOAD_XOR_I16_POSTRA
    0U,	// ATOMIC_LOAD_XOR_I32
    0U,	// ATOMIC_LOAD_XOR_I32_POSTRA
    0U,	// ATOMIC_LOAD_XOR_I64
    0U,	// ATOMIC_LOAD_XOR_I64_POSTRA
    0U,	// ATOMIC_LOAD_XOR_I8
    0U,	// ATOMIC_LOAD_XOR_I8_POSTRA
    0U,	// ATOMIC_SWAP_I16
    0U,	// ATOMIC_SWAP_I16_POSTRA
    0U,	// ATOMIC_SWAP_I32
    0U,	// ATOMIC_SWAP_I32_POSTRA
    0U,	// ATOMIC_SWAP_I64
    0U,	// ATOMIC_SWAP_I64_POSTRA
    0U,	// ATOMIC_SWAP_I8
    0U,	// ATOMIC_SWAP_I8_POSTRA
    0U,	// B
    0U,	// BAL_BR
    0U,	// BAL_BR_MM
    0U,	// BEQLImmMacro
    0U,	// BGE
    0U,	// BGEImmMacro
    0U,	// BGEL
    0U,	// BGELImmMacro
    0U,	// BGEU
    0U,	// BGEUImmMacro
    0U,	// BGEUL
    0U,	// BGEULImmMacro
    0U,	// BGT
    0U,	// BGTImmMacro
    0U,	// BGTL
    0U,	// BGTLImmMacro
    0U,	// BGTU
    0U,	// BGTUImmMacro
    0U,	// BGTUL
    0U,	// BGTULImmMacro
    0U,	// BLE
    0U,	// BLEImmMacro
    0U,	// BLEL
    0U,	// BLELImmMacro
    0U,	// BLEU
    0U,	// BLEUImmMacro
    0U,	// BLEUL
    0U,	// BLEULImmMacro
    0U,	// BLT
    0U,	// BLTImmMacro
    0U,	// BLTL
    0U,	// BLTLImmMacro
    0U,	// BLTU
    0U,	// BLTUImmMacro
    0U,	// BLTUL
    0U,	// BLTULImmMacro
    0U,	// BNELImmMacro
    0U,	// BPOSGE32_PSEUDO
    0U,	// BSEL_D_PSEUDO
    0U,	// BSEL_FD_PSEUDO
    0U,	// BSEL_FW_PSEUDO
    0U,	// BSEL_H_PSEUDO
    0U,	// BSEL_W_PSEUDO
    0U,	// B_MM
    0U,	// B_MMR6_Pseudo
    0U,	// B_MM_Pseudo
    0U,	// BeqImm
    0U,	// BneImm
    0U,	// BteqzT8CmpX16
    0U,	// BteqzT8CmpiX16
    0U,	// BteqzT8SltX16
    0U,	// BteqzT8SltiX16
    0U,	// BteqzT8SltiuX16
    0U,	// BteqzT8SltuX16
    0U,	// BtnezT8CmpX16
    0U,	// BtnezT8CmpiX16
    0U,	// BtnezT8SltX16
    0U,	// BtnezT8SltiX16
    0U,	// BtnezT8SltiuX16
    0U,	// BtnezT8SltuX16
    0U,	// BuildPairF64
    0U,	// BuildPairF64_64
    0U,	// CFTC1
    0U,	// CONSTPOOL_ENTRY
    0U,	// COPY_FD_PSEUDO
    0U,	// COPY_FW_PSEUDO
    0U,	// CTTC1
    0U,	// Constant32
    4U,	// DMULImmMacro
    4U,	// DMULMacro
    4U,	// DMULOMacro
    4U,	// DMULOUMacro
    4U,	// DROL
    4U,	// DROLImm
    4U,	// DROR
    4U,	// DRORImm
    4U,	// DSDivIMacro
    4U,	// DSDivMacro
    4U,	// DSRemIMacro
    4U,	// DSRemMacro
    4U,	// DUDivIMacro
    4U,	// DUDivMacro
    4U,	// DURemIMacro
    4U,	// DURemMacro
    0U,	// ERet
    0U,	// ExtractElementF64
    0U,	// ExtractElementF64_64
    0U,	// FABS_D
    0U,	// FABS_W
    0U,	// FEXP2_D_1_PSEUDO
    0U,	// FEXP2_W_1_PSEUDO
    0U,	// FILL_FD_PSEUDO
    0U,	// FILL_FW_PSEUDO
    0U,	// GotPrologue16
    0U,	// INSERT_B_VIDX64_PSEUDO
    0U,	// INSERT_B_VIDX_PSEUDO
    0U,	// INSERT_D_VIDX64_PSEUDO
    0U,	// INSERT_D_VIDX_PSEUDO
    0U,	// INSERT_FD_PSEUDO
    0U,	// INSERT_FD_VIDX64_PSEUDO
    0U,	// INSERT_FD_VIDX_PSEUDO
    0U,	// INSERT_FW_PSEUDO
    0U,	// INSERT_FW_VIDX64_PSEUDO
    0U,	// INSERT_FW_VIDX_PSEUDO
    0U,	// INSERT_H_VIDX64_PSEUDO
    0U,	// INSERT_H_VIDX_PSEUDO
    0U,	// INSERT_W_VIDX64_PSEUDO
    0U,	// INSERT_W_VIDX_PSEUDO
    0U,	// JALR64Pseudo
    0U,	// JALRHB64Pseudo
    0U,	// JALRHBPseudo
    0U,	// JALRPseudo
    0U,	// JAL_MMR6
    0U,	// JalOneReg
    0U,	// JalTwoReg
    0U,	// LDMacro
    0U,	// LDR_D
    0U,	// LDR_W
    0U,	// LD_F16
    0U,	// LOAD_ACC128
    0U,	// LOAD_ACC64
    0U,	// LOAD_ACC64DSP
    0U,	// LOAD_CCOND_DSP
    0U,	// LONG_BRANCH_ADDiu
    0U,	// LONG_BRANCH_ADDiu2Op
    0U,	// LONG_BRANCH_DADDiu
    0U,	// LONG_BRANCH_DADDiu2Op
    0U,	// LONG_BRANCH_LUi
    0U,	// LONG_BRANCH_LUi2Op
    0U,	// LONG_BRANCH_LUi2Op_64
    0U,	// LWM_MM
    0U,	// LoadAddrImm32
    0U,	// LoadAddrImm64
    0U,	// LoadAddrReg32
    0U,	// LoadAddrReg64
    0U,	// LoadImm32
    0U,	// LoadImm64
    0U,	// LoadImmDoubleFGR
    0U,	// LoadImmDoubleFGR_32
    0U,	// LoadImmDoubleGPR
    0U,	// LoadImmSingleFGR
    0U,	// LoadImmSingleGPR
    0U,	// LwConstant32
    0U,	// MFTACX
    8U,	// MFTC0
    0U,	// MFTC1
    0U,	// MFTDSP
    0U,	// MFTGPR
    0U,	// MFTHC1
    0U,	// MFTHI
    0U,	// MFTLO
    0U,	// MIPSeh_return32
    0U,	// MIPSeh_return64
    0U,	// MSA_FP_EXTEND_D_PSEUDO
    0U,	// MSA_FP_EXTEND_W_PSEUDO
    0U,	// MSA_FP_ROUND_D_PSEUDO
    0U,	// MSA_FP_ROUND_W_PSEUDO
    0U,	// MTTACX
    0U,	// MTTC0
    0U,	// MTTC1
    0U,	// MTTDSP
    0U,	// MTTGPR
    0U,	// MTTHC1
    0U,	// MTTHI
    0U,	// MTTLO
    4U,	// MULImmMacro
    4U,	// MULOMacro
    4U,	// MULOUMacro
    0U,	// MultRxRy16
    0U,	// MultRxRyRz16
    0U,	// MultuRxRy16
    0U,	// MultuRxRyRz16
    0U,	// NOP
    4U,	// NORImm
    4U,	// NORImm64
    0U,	// NOR_V_D_PSEUDO
    0U,	// NOR_V_H_PSEUDO
    0U,	// NOR_V_W_PSEUDO
    0U,	// OR_V_D_PSEUDO
    0U,	// OR_V_H_PSEUDO
    0U,	// OR_V_W_PSEUDO
    0U,	// PseudoCMPU_EQ_QB
    0U,	// PseudoCMPU_LE_QB
    0U,	// PseudoCMPU_LT_QB
    0U,	// PseudoCMP_EQ_PH
    0U,	// PseudoCMP_LE_PH
    0U,	// PseudoCMP_LT_PH
    0U,	// PseudoCVT_D32_W
    0U,	// PseudoCVT_D64_L
    0U,	// PseudoCVT_D64_W
    0U,	// PseudoCVT_S_L
    0U,	// PseudoCVT_S_W
    0U,	// PseudoDMULT
    0U,	// PseudoDMULTu
    0U,	// PseudoDSDIV
    0U,	// PseudoDUDIV
    0U,	// PseudoD_SELECT_I
    0U,	// PseudoD_SELECT_I64
    0U,	// PseudoIndirectBranch
    0U,	// PseudoIndirectBranch64
    0U,	// PseudoIndirectBranch64R6
    0U,	// PseudoIndirectBranchR6
    0U,	// PseudoIndirectBranch_MM
    0U,	// PseudoIndirectBranch_MMR6
    0U,	// PseudoIndirectHazardBranch
    0U,	// PseudoIndirectHazardBranch64
    0U,	// PseudoIndrectHazardBranch64R6
    0U,	// PseudoIndrectHazardBranchR6
    0U,	// PseudoMADD
    0U,	// PseudoMADDU
    0U,	// PseudoMADDU_MM
    0U,	// PseudoMADD_MM
    0U,	// PseudoMFHI
    0U,	// PseudoMFHI64
    0U,	// PseudoMFHI_MM
    0U,	// PseudoMFLO
    0U,	// PseudoMFLO64
    0U,	// PseudoMFLO_MM
    0U,	// PseudoMSUB
    0U,	// PseudoMSUBU
    0U,	// PseudoMSUBU_MM
    0U,	// PseudoMSUB_MM
    0U,	// PseudoMTLOHI
    0U,	// PseudoMTLOHI64
    0U,	// PseudoMTLOHI_DSP
    0U,	// PseudoMTLOHI_MM
    0U,	// PseudoMULT
    0U,	// PseudoMULT_MM
    0U,	// PseudoMULTu
    0U,	// PseudoMULTu_MM
    0U,	// PseudoPICK_PH
    0U,	// PseudoPICK_QB
    0U,	// PseudoReturn
    0U,	// PseudoReturn64
    0U,	// PseudoSDIV
    0U,	// PseudoSELECTFP_F_D32
    0U,	// PseudoSELECTFP_F_D64
    0U,	// PseudoSELECTFP_F_I
    0U,	// PseudoSELECTFP_F_I64
    0U,	// PseudoSELECTFP_F_S
    0U,	// PseudoSELECTFP_T_D32
    0U,	// PseudoSELECTFP_T_D64
    0U,	// PseudoSELECTFP_T_I
    0U,	// PseudoSELECTFP_T_I64
    0U,	// PseudoSELECTFP_T_S
    0U,	// PseudoSELECT_D32
    0U,	// PseudoSELECT_D64
    0U,	// PseudoSELECT_I
    0U,	// PseudoSELECT_I64
    0U,	// PseudoSELECT_S
    4U,	// PseudoTRUNC_W_D
    4U,	// PseudoTRUNC_W_D32
    4U,	// PseudoTRUNC_W_S
    0U,	// PseudoUDIV
    4U,	// ROL
    4U,	// ROLImm
    4U,	// ROR
    4U,	// RORImm
    0U,	// RetRA
    0U,	// RetRA16
    0U,	// SDC1_M1
    0U,	// SDIV_MM_Pseudo
    0U,	// SDMacro
    4U,	// SDivIMacro
    4U,	// SDivMacro
    4U,	// SEQIMacro
    4U,	// SEQMacro
    4U,	// SGE
    4U,	// SGEImm
    4U,	// SGEImm64
    4U,	// SGEU
    4U,	// SGEUImm
    4U,	// SGEUImm64
    4U,	// SGTImm
    4U,	// SGTImm64
    4U,	// SGTUImm
    4U,	// SGTUImm64
    4U,	// SLE
    4U,	// SLEImm
    4U,	// SLEImm64
    4U,	// SLEU
    4U,	// SLEUImm
    4U,	// SLEUImm64
    4U,	// SLTImm64
    4U,	// SLTUImm64
    4U,	// SNEIMacro
    4U,	// SNEMacro
    0U,	// SNZ_B_PSEUDO
    0U,	// SNZ_D_PSEUDO
    0U,	// SNZ_H_PSEUDO
    0U,	// SNZ_V_PSEUDO
    0U,	// SNZ_W_PSEUDO
    4U,	// SRemIMacro
    4U,	// SRemMacro
    0U,	// STORE_ACC128
    0U,	// STORE_ACC64
    0U,	// STORE_ACC64DSP
    0U,	// STORE_CCOND_DSP
    0U,	// STR_D
    0U,	// STR_W
    0U,	// ST_F16
    0U,	// SWM_MM
    0U,	// SZ_B_PSEUDO
    0U,	// SZ_D_PSEUDO
    0U,	// SZ_H_PSEUDO
    0U,	// SZ_V_PSEUDO
    0U,	// SZ_W_PSEUDO
    0U,	// SaaAddr
    0U,	// SaadAddr
    0U,	// SelBeqZ
    0U,	// SelBneZ
    0U,	// SelTBteqZCmp
    0U,	// SelTBteqZCmpi
    0U,	// SelTBteqZSlt
    0U,	// SelTBteqZSlti
    0U,	// SelTBteqZSltiu
    0U,	// SelTBteqZSltu
    0U,	// SelTBtneZCmp
    0U,	// SelTBtneZCmpi
    0U,	// SelTBtneZSlt
    0U,	// SelTBtneZSlti
    0U,	// SelTBtneZSltiu
    0U,	// SelTBtneZSltu
    0U,	// SltCCRxRy16
    0U,	// SltiCCRxImmX16
    0U,	// SltiuCCRxImmX16
    0U,	// SltuCCRxRy16
    0U,	// SltuRxRyRz16
    0U,	// TAILCALL
    0U,	// TAILCALL64R6REG
    0U,	// TAILCALLHB64R6REG
    0U,	// TAILCALLHBR6REG
    0U,	// TAILCALLR6REG
    0U,	// TAILCALLREG
    0U,	// TAILCALLREG64
    0U,	// TAILCALLREGHB
    0U,	// TAILCALLREGHB64
    0U,	// TAILCALLREG_MM
    0U,	// TAILCALLREG_MMR6
    0U,	// TAILCALL_MM
    0U,	// TAILCALL_MMR6
    0U,	// TRAP
    0U,	// TRAP_MM
    0U,	// UDIV_MM_Pseudo
    4U,	// UDivIMacro
    4U,	// UDivMacro
    4U,	// URemIMacro
    4U,	// URemMacro
    0U,	// Ulh
    0U,	// Ulhu
    0U,	// Ulw
    0U,	// Ush
    0U,	// Usw
    0U,	// XOR_V_D_PSEUDO
    0U,	// XOR_V_H_PSEUDO
    0U,	// XOR_V_W_PSEUDO
    0U,	// ABSQ_S_PH
    0U,	// ABSQ_S_PH_MM
    0U,	// ABSQ_S_QB
    0U,	// ABSQ_S_QB_MMR2
    0U,	// ABSQ_S_W
    0U,	// ABSQ_S_W_MM
    4U,	// ADD
    0U,	// ADDIUPC
    0U,	// ADDIUPC_MM
    0U,	// ADDIUPC_MMR6
    0U,	// ADDIUR1SP_MM
    4U,	// ADDIUR2_MM
    0U,	// ADDIUS5_MM
    0U,	// ADDIUSP_MM
    4U,	// ADDIU_MMR6
    4U,	// ADDQH_PH
    4U,	// ADDQH_PH_MMR2
    4U,	// ADDQH_R_PH
    4U,	// ADDQH_R_PH_MMR2
    4U,	// ADDQH_R_W
    4U,	// ADDQH_R_W_MMR2
    4U,	// ADDQH_W
    4U,	// ADDQH_W_MMR2
    4U,	// ADDQ_PH
    4U,	// ADDQ_PH_MM
    4U,	// ADDQ_S_PH
    4U,	// ADDQ_S_PH_MM
    4U,	// ADDQ_S_W
    4U,	// ADDQ_S_W_MM
    4U,	// ADDR_PS64
    4U,	// ADDSC
    4U,	// ADDSC_MM
    4U,	// ADDS_A_B
    4U,	// ADDS_A_D
    4U,	// ADDS_A_H
    4U,	// ADDS_A_W
    4U,	// ADDS_S_B
    4U,	// ADDS_S_D
    4U,	// ADDS_S_H
    4U,	// ADDS_S_W
    4U,	// ADDS_U_B
    4U,	// ADDS_U_D
    4U,	// ADDS_U_H
    4U,	// ADDS_U_W
    4U,	// ADDU16_MM
    4U,	// ADDU16_MMR6
    4U,	// ADDUH_QB
    4U,	// ADDUH_QB_MMR2
    4U,	// ADDUH_R_QB
    4U,	// ADDUH_R_QB_MMR2
    4U,	// ADDU_MMR6
    4U,	// ADDU_PH
    4U,	// ADDU_PH_MMR2
    4U,	// ADDU_QB
    4U,	// ADDU_QB_MM
    4U,	// ADDU_S_PH
    4U,	// ADDU_S_PH_MMR2
    4U,	// ADDU_S_QB
    4U,	// ADDU_S_QB_MM
    12U,	// ADDVI_B
    12U,	// ADDVI_D
    12U,	// ADDVI_H
    12U,	// ADDVI_W
    4U,	// ADDV_B
    4U,	// ADDV_D
    4U,	// ADDV_H
    4U,	// ADDV_W
    4U,	// ADDWC
    4U,	// ADDWC_MM
    4U,	// ADD_A_B
    4U,	// ADD_A_D
    4U,	// ADD_A_H
    4U,	// ADD_A_W
    4U,	// ADD_MM
    4U,	// ADD_MMR6
    4U,	// ADDi
    4U,	// ADDi_MM
    4U,	// ADDiu
    4U,	// ADDiu_MM
    4U,	// ADDu
    4U,	// ADDu_MM
    132U,	// ALIGN
    132U,	// ALIGN_MMR6
    0U,	// ALUIPC
    0U,	// ALUIPC_MMR6
    4U,	// AND
    0U,	// AND16_MM
    0U,	// AND16_MMR6
    4U,	// AND64
    4U,	// ANDI16_MM
    4U,	// ANDI16_MMR6
    16U,	// ANDI_B
    20U,	// ANDI_MMR6
    4U,	// AND_MM
    4U,	// AND_MMR6
    4U,	// AND_V
    20U,	// ANDi
    20U,	// ANDi64
    20U,	// ANDi_MM
    12U,	// APPEND
    12U,	// APPEND_MMR2
    4U,	// ASUB_S_B
    4U,	// ASUB_S_D
    4U,	// ASUB_S_H
    4U,	// ASUB_S_W
    4U,	// ASUB_U_B
    4U,	// ASUB_U_D
    4U,	// ASUB_U_H
    4U,	// ASUB_U_W
    20U,	// AUI
    0U,	// AUIPC
    0U,	// AUIPC_MMR6
    20U,	// AUI_MMR6
    4U,	// AVER_S_B
    4U,	// AVER_S_D
    4U,	// AVER_S_H
    4U,	// AVER_S_W
    4U,	// AVER_U_B
    4U,	// AVER_U_D
    4U,	// AVER_U_H
    4U,	// AVER_U_W
    4U,	// AVE_S_B
    4U,	// AVE_S_D
    4U,	// AVE_S_H
    4U,	// AVE_S_W
    4U,	// AVE_U_B
    4U,	// AVE_U_D
    4U,	// AVE_U_H
    4U,	// AVE_U_W
    0U,	// AddiuRxImmX16
    0U,	// AddiuRxPcImmX16
    1U,	// AddiuRxRxImm16
    0U,	// AddiuRxRxImmX16
    0U,	// AddiuRxRyOffMemX16
    0U,	// AddiuSpImm16
    0U,	// AddiuSpImmX16
    4U,	// AdduRxRyRz16
    0U,	// AndRxRxRy16
    0U,	// B16_MM
    4U,	// BADDu
    0U,	// BAL
    0U,	// BALC
    0U,	// BALC_MMR6
    24U,	// BALIGN
    24U,	// BALIGN_MMR2
    0U,	// BBIT0
    0U,	// BBIT032
    0U,	// BBIT1
    0U,	// BBIT132
    0U,	// BC
    0U,	// BC16_MMR6
    0U,	// BC1EQZ
    0U,	// BC1EQZC_MMR6
    0U,	// BC1F
    0U,	// BC1FL
    0U,	// BC1F_MM
    0U,	// BC1NEZ
    0U,	// BC1NEZC_MMR6
    0U,	// BC1T
    0U,	// BC1TL
    0U,	// BC1T_MM
    0U,	// BC2EQZ
    0U,	// BC2EQZC_MMR6
    0U,	// BC2NEZ
    0U,	// BC2NEZC_MMR6
    8U,	// BCLRI_B
    28U,	// BCLRI_D
    32U,	// BCLRI_H
    12U,	// BCLRI_W
    4U,	// BCLR_B
    4U,	// BCLR_D
    4U,	// BCLR_H
    4U,	// BCLR_W
    0U,	// BC_MMR6
    0U,	// BEQ
    0U,	// BEQ64
    0U,	// BEQC
    0U,	// BEQC64
    0U,	// BEQC_MMR6
    0U,	// BEQL
    0U,	// BEQZ16_MM
    0U,	// BEQZALC
    0U,	// BEQZALC_MMR6
    0U,	// BEQZC
    0U,	// BEQZC16_MMR6
    0U,	// BEQZC64
    0U,	// BEQZC_MM
    0U,	// BEQZC_MMR6
    0U,	// BEQ_MM
    0U,	// BGEC
    0U,	// BGEC64
    0U,	// BGEC_MMR6
    0U,	// BGEUC
    0U,	// BGEUC64
    0U,	// BGEUC_MMR6
    0U,	// BGEZ
    0U,	// BGEZ64
    0U,	// BGEZAL
    0U,	// BGEZALC
    0U,	// BGEZALC_MMR6
    0U,	// BGEZALL
    0U,	// BGEZALS_MM
    0U,	// BGEZAL_MM
    0U,	// BGEZC
    0U,	// BGEZC64
    0U,	// BGEZC_MMR6
    0U,	// BGEZL
    0U,	// BGEZ_MM
    0U,	// BGTZ
    0U,	// BGTZ64
    0U,	// BGTZALC
    0U,	// BGTZALC_MMR6
    0U,	// BGTZC
    0U,	// BGTZC64
    0U,	// BGTZC_MMR6
    0U,	// BGTZL
    0U,	// BGTZ_MM
    36U,	// BINSLI_B
    40U,	// BINSLI_D
    44U,	// BINSLI_H
    48U,	// BINSLI_W
    52U,	// BINSL_B
    52U,	// BINSL_D
    52U,	// BINSL_H
    52U,	// BINSL_W
    36U,	// BINSRI_B
    40U,	// BINSRI_D
    44U,	// BINSRI_H
    48U,	// BINSRI_W
    52U,	// BINSR_B
    52U,	// BINSR_D
    52U,	// BINSR_H
    52U,	// BINSR_W
    0U,	// BITREV
    0U,	// BITREV_MM
    0U,	// BITSWAP
    0U,	// BITSWAP_MMR6
    0U,	// BLEZ
    0U,	// BLEZ64
    0U,	// BLEZALC
    0U,	// BLEZALC_MMR6
    0U,	// BLEZC
    0U,	// BLEZC64
    0U,	// BLEZC_MMR6
    0U,	// BLEZL
    0U,	// BLEZ_MM
    0U,	// BLTC
    0U,	// BLTC64
    0U,	// BLTC_MMR6
    0U,	// BLTUC
    0U,	// BLTUC64
    0U,	// BLTUC_MMR6
    0U,	// BLTZ
    0U,	// BLTZ64
    0U,	// BLTZAL
    0U,	// BLTZALC
    0U,	// BLTZALC_MMR6
    0U,	// BLTZALL
    0U,	// BLTZALS_MM
    0U,	// BLTZAL_MM
    0U,	// BLTZC
    0U,	// BLTZC64
    0U,	// BLTZC_MMR6
    0U,	// BLTZL
    0U,	// BLTZ_MM
    56U,	// BMNZI_B
    52U,	// BMNZ_V
    56U,	// BMZI_B
    52U,	// BMZ_V
    0U,	// BNE
    0U,	// BNE64
    0U,	// BNEC
    0U,	// BNEC64
    0U,	// BNEC_MMR6
    8U,	// BNEGI_B
    28U,	// BNEGI_D
    32U,	// BNEGI_H
    12U,	// BNEGI_W
    4U,	// BNEG_B
    4U,	// BNEG_D
    4U,	// BNEG_H
    4U,	// BNEG_W
    0U,	// BNEL
    0U,	// BNEZ16_MM
    0U,	// BNEZALC
    0U,	// BNEZALC_MMR6
    0U,	// BNEZC
    0U,	// BNEZC16_MMR6
    0U,	// BNEZC64
    0U,	// BNEZC_MM
    0U,	// BNEZC_MMR6
    0U,	// BNE_MM
    0U,	// BNVC
    0U,	// BNVC_MMR6
    0U,	// BNZ_B
    0U,	// BNZ_D
    0U,	// BNZ_H
    0U,	// BNZ_V
    0U,	// BNZ_W
    0U,	// BOVC
    0U,	// BOVC_MMR6
    0U,	// BPOSGE32
    0U,	// BPOSGE32C_MMR3
    0U,	// BPOSGE32_MM
    0U,	// BREAK
    0U,	// BREAK16_MM
    0U,	// BREAK16_MMR6
    0U,	// BREAK_MM
    0U,	// BREAK_MMR6
    56U,	// BSELI_B
    52U,	// BSEL_V
    8U,	// BSETI_B
    28U,	// BSETI_D
    32U,	// BSETI_H
    12U,	// BSETI_W
    4U,	// BSET_B
    4U,	// BSET_D
    4U,	// BSET_H
    4U,	// BSET_W
    0U,	// BZ_B
    0U,	// BZ_D
    0U,	// BZ_H
    0U,	// BZ_V
    0U,	// BZ_W
    1U,	// BeqzRxImm16
    0U,	// BeqzRxImmX16
    0U,	// Bimm16
    0U,	// BimmX16
    1U,	// BnezRxImm16
    0U,	// BnezRxImmX16
    0U,	// Break16
    0U,	// Bteqz16
    0U,	// BteqzX16
    0U,	// Btnez16
    0U,	// BtnezX16
    0U,	// CACHE
    0U,	// CACHEE
    0U,	// CACHEE_MM
    0U,	// CACHE_MM
    0U,	// CACHE_MMR6
    0U,	// CACHE_R6
    0U,	// CEIL_L_D64
    0U,	// CEIL_L_D_MMR6
    0U,	// CEIL_L_S
    0U,	// CEIL_L_S_MMR6
    0U,	// CEIL_W_D32
    0U,	// CEIL_W_D64
    0U,	// CEIL_W_D_MMR6
    0U,	// CEIL_W_MM
    0U,	// CEIL_W_S
    0U,	// CEIL_W_S_MM
    0U,	// CEIL_W_S_MMR6
    4U,	// CEQI_B
    4U,	// CEQI_D
    4U,	// CEQI_H
    4U,	// CEQI_W
    4U,	// CEQ_B
    4U,	// CEQ_D
    4U,	// CEQ_H
    4U,	// CEQ_W
    0U,	// CFC1
    0U,	// CFC1_MM
    0U,	// CFC2_MM
    0U,	// CFCMSA
    1164U,	// CINS
    1164U,	// CINS32
    1164U,	// CINS64_32
    1164U,	// CINS_i32
    0U,	// CLASS_D
    0U,	// CLASS_D_MMR6
    0U,	// CLASS_S
    0U,	// CLASS_S_MMR6
    4U,	// CLEI_S_B
    4U,	// CLEI_S_D
    4U,	// CLEI_S_H
    4U,	// CLEI_S_W
    12U,	// CLEI_U_B
    12U,	// CLEI_U_D
    12U,	// CLEI_U_H
    12U,	// CLEI_U_W
    4U,	// CLE_S_B
    4U,	// CLE_S_D
    4U,	// CLE_S_H
    4U,	// CLE_S_W
    4U,	// CLE_U_B
    4U,	// CLE_U_D
    4U,	// CLE_U_H
    4U,	// CLE_U_W
    0U,	// CLO
    0U,	// CLO_MM
    0U,	// CLO_MMR6
    0U,	// CLO_R6
    4U,	// CLTI_S_B
    4U,	// CLTI_S_D
    4U,	// CLTI_S_H
    4U,	// CLTI_S_W
    12U,	// CLTI_U_B
    12U,	// CLTI_U_D
    12U,	// CLTI_U_H
    12U,	// CLTI_U_W
    4U,	// CLT_S_B
    4U,	// CLT_S_D
    4U,	// CLT_S_H
    4U,	// CLT_S_W
    4U,	// CLT_U_B
    4U,	// CLT_U_D
    4U,	// CLT_U_H
    4U,	// CLT_U_W
    0U,	// CLZ
    0U,	// CLZ_MM
    0U,	// CLZ_MMR6
    0U,	// CLZ_R6
    4U,	// CMPGDU_EQ_QB
    4U,	// CMPGDU_EQ_QB_MMR2
    4U,	// CMPGDU_LE_QB
    4U,	// CMPGDU_LE_QB_MMR2
    4U,	// CMPGDU_LT_QB
    4U,	// CMPGDU_LT_QB_MMR2
    4U,	// CMPGU_EQ_QB
    4U,	// CMPGU_EQ_QB_MM
    4U,	// CMPGU_LE_QB
    4U,	// CMPGU_LE_QB_MM
    4U,	// CMPGU_LT_QB
    4U,	// CMPGU_LT_QB_MM
    0U,	// CMPU_EQ_QB
    0U,	// CMPU_EQ_QB_MM
    0U,	// CMPU_LE_QB
    0U,	// CMPU_LE_QB_MM
    0U,	// CMPU_LT_QB
    0U,	// CMPU_LT_QB_MM
    4U,	// CMP_AF_D_MMR6
    4U,	// CMP_AF_S_MMR6
    4U,	// CMP_EQ_D
    4U,	// CMP_EQ_D_MMR6
    0U,	// CMP_EQ_PH
    0U,	// CMP_EQ_PH_MM
    4U,	// CMP_EQ_S
    4U,	// CMP_EQ_S_MMR6
    4U,	// CMP_F_D
    4U,	// CMP_F_S
    4U,	// CMP_LE_D
    4U,	// CMP_LE_D_MMR6
    0U,	// CMP_LE_PH
    0U,	// CMP_LE_PH_MM
    4U,	// CMP_LE_S
    4U,	// CMP_LE_S_MMR6
    4U,	// CMP_LT_D
    4U,	// CMP_LT_D_MMR6
    0U,	// CMP_LT_PH
    0U,	// CMP_LT_PH_MM
    4U,	// CMP_LT_S
    4U,	// CMP_LT_S_MMR6
    4U,	// CMP_SAF_D
    4U,	// CMP_SAF_D_MMR6
    4U,	// CMP_SAF_S
    4U,	// CMP_SAF_S_MMR6
    4U,	// CMP_SEQ_D
    4U,	// CMP_SEQ_D_MMR6
    4U,	// CMP_SEQ_S
    4U,	// CMP_SEQ_S_MMR6
    4U,	// CMP_SLE_D
    4U,	// CMP_SLE_D_MMR6
    4U,	// CMP_SLE_S
    4U,	// CMP_SLE_S_MMR6
    4U,	// CMP_SLT_D
    4U,	// CMP_SLT_D_MMR6
    4U,	// CMP_SLT_S
    4U,	// CMP_SLT_S_MMR6
    4U,	// CMP_SUEQ_D
    4U,	// CMP_SUEQ_D_MMR6
    4U,	// CMP_SUEQ_S
    4U,	// CMP_SUEQ_S_MMR6
    4U,	// CMP_SULE_D
    4U,	// CMP_SULE_D_MMR6
    4U,	// CMP_SULE_S
    4U,	// CMP_SULE_S_MMR6
    4U,	// CMP_SULT_D
    4U,	// CMP_SULT_D_MMR6
    4U,	// CMP_SULT_S
    4U,	// CMP_SULT_S_MMR6
    4U,	// CMP_SUN_D
    4U,	// CMP_SUN_D_MMR6
    4U,	// CMP_SUN_S
    4U,	// CMP_SUN_S_MMR6
    4U,	// CMP_UEQ_D
    4U,	// CMP_UEQ_D_MMR6
    4U,	// CMP_UEQ_S
    4U,	// CMP_UEQ_S_MMR6
    4U,	// CMP_ULE_D
    4U,	// CMP_ULE_D_MMR6
    4U,	// CMP_ULE_S
    4U,	// CMP_ULE_S_MMR6
    4U,	// CMP_ULT_D
    4U,	// CMP_ULT_D_MMR6
    4U,	// CMP_ULT_S
    4U,	// CMP_ULT_S_MMR6
    4U,	// CMP_UN_D
    4U,	// CMP_UN_D_MMR6
    4U,	// CMP_UN_S
    4U,	// CMP_UN_S_MMR6
    289U,	// COPY_S_B
    317U,	// COPY_S_D
    265U,	// COPY_S_H
    281U,	// COPY_S_W
    289U,	// COPY_U_B
    265U,	// COPY_U_H
    281U,	// COPY_U_W
    4U,	// CRC32B
    4U,	// CRC32CB
    4U,	// CRC32CD
    4U,	// CRC32CH
    4U,	// CRC32CW
    4U,	// CRC32D
    4U,	// CRC32H
    4U,	// CRC32W
    0U,	// CTC1
    0U,	// CTC1_MM
    0U,	// CTC2_MM
    0U,	// CTCMSA
    0U,	// CVT_D32_S
    0U,	// CVT_D32_S_MM
    0U,	// CVT_D32_W
    0U,	// CVT_D32_W_MM
    0U,	// CVT_D64_L
    0U,	// CVT_D64_S
    0U,	// CVT_D64_S_MM
    0U,	// CVT_D64_W
    0U,	// CVT_D64_W_MM
    0U,	// CVT_D_L_MMR6
    0U,	// CVT_L_D64
    0U,	// CVT_L_D64_MM
    0U,	// CVT_L_D_MMR6
    0U,	// CVT_L_S
    0U,	// CVT_L_S_MM
    0U,	// CVT_L_S_MMR6
    0U,	// CVT_PS_PW64
    4U,	// CVT_PS_S64
    0U,	// CVT_PW_PS64
    0U,	// CVT_S_D32
    0U,	// CVT_S_D32_MM
    0U,	// CVT_S_D64
    0U,	// CVT_S_D64_MM
    0U,	// CVT_S_L
    0U,	// CVT_S_L_MMR6
    0U,	// CVT_S_PL64
    0U,	// CVT_S_PU64
    0U,	// CVT_S_W
    0U,	// CVT_S_W_MM
    0U,	// CVT_S_W_MMR6
    0U,	// CVT_W_D32
    0U,	// CVT_W_D32_MM
    0U,	// CVT_W_D64
    0U,	// CVT_W_D64_MM
    0U,	// CVT_W_S
    0U,	// CVT_W_S_MM
    0U,	// CVT_W_S_MMR6
    4U,	// C_EQ_D32
    4U,	// C_EQ_D32_MM
    4U,	// C_EQ_D64
    4U,	// C_EQ_D64_MM
    4U,	// C_EQ_S
    4U,	// C_EQ_S_MM
    4U,	// C_F_D32
    4U,	// C_F_D32_MM
    4U,	// C_F_D64
    4U,	// C_F_D64_MM
    4U,	// C_F_S
    4U,	// C_F_S_MM
    4U,	// C_LE_D32
    4U,	// C_LE_D32_MM
    4U,	// C_LE_D64
    4U,	// C_LE_D64_MM
    4U,	// C_LE_S
    4U,	// C_LE_S_MM
    4U,	// C_LT_D32
    4U,	// C_LT_D32_MM
    4U,	// C_LT_D64
    4U,	// C_LT_D64_MM
    4U,	// C_LT_S
    4U,	// C_LT_S_MM
    4U,	// C_NGE_D32
    4U,	// C_NGE_D32_MM
    4U,	// C_NGE_D64
    4U,	// C_NGE_D64_MM
    4U,	// C_NGE_S
    4U,	// C_NGE_S_MM
    4U,	// C_NGLE_D32
    4U,	// C_NGLE_D32_MM
    4U,	// C_NGLE_D64
    4U,	// C_NGLE_D64_MM
    4U,	// C_NGLE_S
    4U,	// C_NGLE_S_MM
    4U,	// C_NGL_D32
    4U,	// C_NGL_D32_MM
    4U,	// C_NGL_D64
    4U,	// C_NGL_D64_MM
    4U,	// C_NGL_S
    4U,	// C_NGL_S_MM
    4U,	// C_NGT_D32
    4U,	// C_NGT_D32_MM
    4U,	// C_NGT_D64
    4U,	// C_NGT_D64_MM
    4U,	// C_NGT_S
    4U,	// C_NGT_S_MM
    4U,	// C_OLE_D32
    4U,	// C_OLE_D32_MM
    4U,	// C_OLE_D64
    4U,	// C_OLE_D64_MM
    4U,	// C_OLE_S
    4U,	// C_OLE_S_MM
    4U,	// C_OLT_D32
    4U,	// C_OLT_D32_MM
    4U,	// C_OLT_D64
    4U,	// C_OLT_D64_MM
    4U,	// C_OLT_S
    4U,	// C_OLT_S_MM
    4U,	// C_SEQ_D32
    4U,	// C_SEQ_D32_MM
    4U,	// C_SEQ_D64
    4U,	// C_SEQ_D64_MM
    4U,	// C_SEQ_S
    4U,	// C_SEQ_S_MM
    4U,	// C_SF_D32
    4U,	// C_SF_D32_MM
    4U,	// C_SF_D64
    4U,	// C_SF_D64_MM
    4U,	// C_SF_S
    4U,	// C_SF_S_MM
    4U,	// C_UEQ_D32
    4U,	// C_UEQ_D32_MM
    4U,	// C_UEQ_D64
    4U,	// C_UEQ_D64_MM
    4U,	// C_UEQ_S
    4U,	// C_UEQ_S_MM
    4U,	// C_ULE_D32
    4U,	// C_ULE_D32_MM
    4U,	// C_ULE_D64
    4U,	// C_ULE_D64_MM
    4U,	// C_ULE_S
    4U,	// C_ULE_S_MM
    4U,	// C_ULT_D32
    4U,	// C_ULT_D32_MM
    4U,	// C_ULT_D64
    4U,	// C_ULT_D64_MM
    4U,	// C_ULT_S
    4U,	// C_ULT_S_MM
    4U,	// C_UN_D32
    4U,	// C_UN_D32_MM
    4U,	// C_UN_D64
    4U,	// C_UN_D64_MM
    4U,	// C_UN_S
    4U,	// C_UN_S_MM
    0U,	// CmpRxRy16
    1U,	// CmpiRxImm16
    0U,	// CmpiRxImmX16
    4U,	// DADD
    4U,	// DADDi
    4U,	// DADDiu
    4U,	// DADDu
    20U,	// DAHI
    2180U,	// DALIGN
    20U,	// DATI
    20U,	// DAUI
    0U,	// DBITSWAP
    0U,	// DCLO
    0U,	// DCLO_R6
    0U,	// DCLZ
    0U,	// DCLZ_R6
    4U,	// DDIV
    4U,	// DDIVU
    0U,	// DERET
    0U,	// DERET_MM
    0U,	// DERET_MMR6
    3228U,	// DEXT
    4252U,	// DEXT64_32
    5260U,	// DEXTM
    448U,	// DEXTU
    0U,	// DI
    6300U,	// DINS
    7308U,	// DINSM
    576U,	// DINSU
    4U,	// DIV
    4U,	// DIVU
    4U,	// DIVU_MMR6
    4U,	// DIV_MMR6
    4U,	// DIV_S_B
    4U,	// DIV_S_D
    4U,	// DIV_S_H
    4U,	// DIV_S_W
    4U,	// DIV_U_B
    4U,	// DIV_U_D
    4U,	// DIV_U_H
    4U,	// DIV_U_W
    0U,	// DI_MM
    0U,	// DI_MMR6
    8324U,	// DLSA
    8324U,	// DLSA_R6
    8U,	// DMFC0
    0U,	// DMFC1
    8U,	// DMFC2
    0U,	// DMFC2_OCTEON
    8U,	// DMFGC0
    4U,	// DMOD
    4U,	// DMODU
    0U,	// DMT
    0U,	// DMTC0
    0U,	// DMTC1
    0U,	// DMTC2
    0U,	// DMTC2_OCTEON
    0U,	// DMTGC0
    4U,	// DMUH
    4U,	// DMUHU
    4U,	// DMUL
    0U,	// DMULT
    0U,	// DMULTu
    4U,	// DMULU
    4U,	// DMUL_R6
    4U,	// DOTP_S_D
    4U,	// DOTP_S_H
    4U,	// DOTP_S_W
    4U,	// DOTP_U_D
    4U,	// DOTP_U_H
    4U,	// DOTP_U_W
    52U,	// DPADD_S_D
    52U,	// DPADD_S_H
    52U,	// DPADD_S_W
    52U,	// DPADD_U_D
    52U,	// DPADD_U_H
    52U,	// DPADD_U_W
    4U,	// DPAQX_SA_W_PH
    4U,	// DPAQX_SA_W_PH_MMR2
    4U,	// DPAQX_S_W_PH
    4U,	// DPAQX_S_W_PH_MMR2
    4U,	// DPAQ_SA_L_W
    4U,	// DPAQ_SA_L_W_MM
    4U,	// DPAQ_S_W_PH
    4U,	// DPAQ_S_W_PH_MM
    4U,	// DPAU_H_QBL
    4U,	// DPAU_H_QBL_MM
    4U,	// DPAU_H_QBR
    4U,	// DPAU_H_QBR_MM
    4U,	// DPAX_W_PH
    4U,	// DPAX_W_PH_MMR2
    4U,	// DPA_W_PH
    4U,	// DPA_W_PH_MMR2
    0U,	// DPOP
    4U,	// DPSQX_SA_W_PH
    4U,	// DPSQX_SA_W_PH_MMR2
    4U,	// DPSQX_S_W_PH
    4U,	// DPSQX_S_W_PH_MMR2
    4U,	// DPSQ_SA_L_W
    4U,	// DPSQ_SA_L_W_MM
    4U,	// DPSQ_S_W_PH
    4U,	// DPSQ_S_W_PH_MM
    52U,	// DPSUB_S_D
    52U,	// DPSUB_S_H
    52U,	// DPSUB_S_W
    52U,	// DPSUB_U_D
    52U,	// DPSUB_U_H
    52U,	// DPSUB_U_W
    4U,	// DPSU_H_QBL
    4U,	// DPSU_H_QBL_MM
    4U,	// DPSU_H_QBR
    4U,	// DPSU_H_QBR_MM
    4U,	// DPSX_W_PH
    4U,	// DPSX_W_PH_MMR2
    4U,	// DPS_W_PH
    4U,	// DPS_W_PH_MMR2
    28U,	// DROTR
    12U,	// DROTR32
    4U,	// DROTRV
    0U,	// DSBH
    0U,	// DSDIV
    0U,	// DSHD
    28U,	// DSLL
    12U,	// DSLL32
    1U,	// DSLL64_32
    4U,	// DSLLV
    28U,	// DSRA
    12U,	// DSRA32
    4U,	// DSRAV
    28U,	// DSRL
    12U,	// DSRL32
    4U,	// DSRLV
    4U,	// DSUB
    4U,	// DSUBu
    0U,	// DUDIV
    0U,	// DVP
    0U,	// DVPE
    0U,	// DVP_MMR6
    0U,	// DivRxRy16
    0U,	// DivuRxRy16
    0U,	// EHB
    0U,	// EHB_MM
    0U,	// EHB_MMR6
    0U,	// EI
    0U,	// EI_MM
    0U,	// EI_MMR6
    0U,	// EMT
    0U,	// ERET
    0U,	// ERETNC
    0U,	// ERETNC_MMR6
    0U,	// ERET_MM
    0U,	// ERET_MMR6
    0U,	// EVP
    0U,	// EVPE
    0U,	// EVP_MMR6
    4236U,	// EXT
    12U,	// EXTP
    12U,	// EXTPDP
    4U,	// EXTPDPV
    4U,	// EXTPDPV_MM
    12U,	// EXTPDP_MM
    4U,	// EXTPV
    4U,	// EXTPV_MM
    12U,	// EXTP_MM
    4U,	// EXTRV_RS_W
    4U,	// EXTRV_RS_W_MM
    4U,	// EXTRV_R_W
    4U,	// EXTRV_R_W_MM
    4U,	// EXTRV_S_H
    4U,	// EXTRV_S_H_MM
    4U,	// EXTRV_W
    4U,	// EXTRV_W_MM
    12U,	// EXTR_RS_W
    12U,	// EXTR_RS_W_MM
    12U,	// EXTR_R_W
    12U,	// EXTR_R_W_MM
    12U,	// EXTR_S_H
    12U,	// EXTR_S_H_MM
    12U,	// EXTR_W
    12U,	// EXTR_W_MM
    1164U,	// EXTS
    1164U,	// EXTS32
    4236U,	// EXT_MM
    4236U,	// EXT_MMR6
    0U,	// FABS_D32
    0U,	// FABS_D32_MM
    0U,	// FABS_D64
    0U,	// FABS_D64_MM
    0U,	// FABS_S
    0U,	// FABS_S_MM
    4U,	// FADD_D
    4U,	// FADD_D32
    4U,	// FADD_D32_MM
    4U,	// FADD_D64
    4U,	// FADD_D64_MM
    4U,	// FADD_PS64
    4U,	// FADD_S
    4U,	// FADD_S_MM
    68U,	// FADD_S_MMR6
    4U,	// FADD_W
    4U,	// FCAF_D
    4U,	// FCAF_W
    4U,	// FCEQ_D
    4U,	// FCEQ_W
    0U,	// FCLASS_D
    0U,	// FCLASS_W
    4U,	// FCLE_D
    4U,	// FCLE_W
    4U,	// FCLT_D
    4U,	// FCLT_W
    0U,	// FCMP_D32
    0U,	// FCMP_D32_MM
    0U,	// FCMP_D64
    0U,	// FCMP_S32
    0U,	// FCMP_S32_MM
    4U,	// FCNE_D
    4U,	// FCNE_W
    4U,	// FCOR_D
    4U,	// FCOR_W
    4U,	// FCUEQ_D
    4U,	// FCUEQ_W
    4U,	// FCULE_D
    4U,	// FCULE_W
    4U,	// FCULT_D
    4U,	// FCULT_W
    4U,	// FCUNE_D
    4U,	// FCUNE_W
    4U,	// FCUN_D
    4U,	// FCUN_W
    4U,	// FDIV_D
    4U,	// FDIV_D32
    4U,	// FDIV_D32_MM
    4U,	// FDIV_D64
    4U,	// FDIV_D64_MM
    4U,	// FDIV_S
    4U,	// FDIV_S_MM
    68U,	// FDIV_S_MMR6
    4U,	// FDIV_W
    4U,	// FEXDO_H
    4U,	// FEXDO_W
    4U,	// FEXP2_D
    4U,	// FEXP2_W
    0U,	// FEXUPL_D
    0U,	// FEXUPL_W
    0U,	// FEXUPR_D
    0U,	// FEXUPR_W
    0U,	// FFINT_S_D
    0U,	// FFINT_S_W
    0U,	// FFINT_U_D
    0U,	// FFINT_U_W
    0U,	// FFQL_D
    0U,	// FFQL_W
    0U,	// FFQR_D
    0U,	// FFQR_W
    0U,	// FILL_B
    0U,	// FILL_D
    0U,	// FILL_H
    0U,	// FILL_W
    0U,	// FLOG2_D
    0U,	// FLOG2_W
    0U,	// FLOOR_L_D64
    0U,	// FLOOR_L_D_MMR6
    0U,	// FLOOR_L_S
    0U,	// FLOOR_L_S_MMR6
    0U,	// FLOOR_W_D32
    0U,	// FLOOR_W_D64
    0U,	// FLOOR_W_D_MMR6
    0U,	// FLOOR_W_MM
    0U,	// FLOOR_W_S
    0U,	// FLOOR_W_S_MM
    0U,	// FLOOR_W_S_MMR6
    52U,	// FMADD_D
    52U,	// FMADD_W
    4U,	// FMAX_A_D
    4U,	// FMAX_A_W
    4U,	// FMAX_D
    4U,	// FMAX_W
    4U,	// FMIN_A_D
    4U,	// FMIN_A_W
    4U,	// FMIN_D
    4U,	// FMIN_W
    0U,	// FMOV_D32
    0U,	// FMOV_D32_MM
    0U,	// FMOV_D64
    0U,	// FMOV_D64_MM
    0U,	// FMOV_D_MMR6
    0U,	// FMOV_S
    0U,	// FMOV_S_MM
    0U,	// FMOV_S_MMR6
    52U,	// FMSUB_D
    52U,	// FMSUB_W
    4U,	// FMUL_D
    4U,	// FMUL_D32
    4U,	// FMUL_D32_MM
    4U,	// FMUL_D64
    4U,	// FMUL_D64_MM
    4U,	// FMUL_PS64
    4U,	// FMUL_S
    4U,	// FMUL_S_MM
    68U,	// FMUL_S_MMR6
    4U,	// FMUL_W
    0U,	// FNEG_D32
    0U,	// FNEG_D32_MM
    0U,	// FNEG_D64
    0U,	// FNEG_D64_MM
    0U,	// FNEG_S
    0U,	// FNEG_S_MM
    0U,	// FNEG_S_MMR6
    1U,	// FORK
    0U,	// FRCP_D
    0U,	// FRCP_W
    0U,	// FRINT_D
    0U,	// FRINT_W
    0U,	// FRSQRT_D
    0U,	// FRSQRT_W
    4U,	// FSAF_D
    4U,	// FSAF_W
    4U,	// FSEQ_D
    4U,	// FSEQ_W
    4U,	// FSLE_D
    4U,	// FSLE_W
    4U,	// FSLT_D
    4U,	// FSLT_W
    4U,	// FSNE_D
    4U,	// FSNE_W
    4U,	// FSOR_D
    4U,	// FSOR_W
    0U,	// FSQRT_D
    0U,	// FSQRT_D32
    0U,	// FSQRT_D32_MM
    0U,	// FSQRT_D64
    0U,	// FSQRT_D64_MM
    0U,	// FSQRT_S
    0U,	// FSQRT_S_MM
    0U,	// FSQRT_W
    4U,	// FSUB_D
    4U,	// FSUB_D32
    4U,	// FSUB_D32_MM
    4U,	// FSUB_D64
    4U,	// FSUB_D64_MM
    4U,	// FSUB_PS64
    4U,	// FSUB_S
    4U,	// FSUB_S_MM
    68U,	// FSUB_S_MMR6
    4U,	// FSUB_W
    4U,	// FSUEQ_D
    4U,	// FSUEQ_W
    4U,	// FSULE_D
    4U,	// FSULE_W
    4U,	// FSULT_D
    4U,	// FSULT_W
    4U,	// FSUNE_D
    4U,	// FSUNE_W
    4U,	// FSUN_D
    4U,	// FSUN_W
    0U,	// FTINT_S_D
    0U,	// FTINT_S_W
    0U,	// FTINT_U_D
    0U,	// FTINT_U_W
    4U,	// FTQ_H
    4U,	// FTQ_W
    0U,	// FTRUNC_S_D
    0U,	// FTRUNC_S_W
    0U,	// FTRUNC_U_D
    0U,	// FTRUNC_U_W
    0U,	// GINVI
    0U,	// GINVI_MMR6
    0U,	// GINVT
    0U,	// GINVT_MMR6
    4U,	// HADD_S_D
    4U,	// HADD_S_H
    4U,	// HADD_S_W
    4U,	// HADD_U_D
    4U,	// HADD_U_H
    4U,	// HADD_U_W
    4U,	// HSUB_S_D
    4U,	// HSUB_S_H
    4U,	// HSUB_S_W
    4U,	// HSUB_U_D
    4U,	// HSUB_U_H
    4U,	// HSUB_U_W
    0U,	// HYPCALL
    0U,	// HYPCALL_MM
    4U,	// ILVEV_B
    4U,	// ILVEV_D
    4U,	// ILVEV_H
    4U,	// ILVEV_W
    4U,	// ILVL_B
    4U,	// ILVL_D
    4U,	// ILVL_H
    4U,	// ILVL_W
    4U,	// ILVOD_B
    4U,	// ILVOD_D
    4U,	// ILVOD_H
    4U,	// ILVOD_W
    4U,	// ILVR_B
    4U,	// ILVR_D
    4U,	// ILVR_H
    4U,	// ILVR_W
    6284U,	// INS
    0U,	// INSERT_B
    0U,	// INSERT_D
    0U,	// INSERT_H
    0U,	// INSERT_W
    0U,	// INSV
    0U,	// INSVE_B
    0U,	// INSVE_D
    0U,	// INSVE_H
    0U,	// INSVE_W
    0U,	// INSV_MM
    6284U,	// INS_MM
    6284U,	// INS_MMR6
    0U,	// J
    0U,	// JAL
    0U,	// JALR
    0U,	// JALR16_MM
    0U,	// JALR64
    0U,	// JALRC16_MMR6
    0U,	// JALRC_HB_MMR6
    0U,	// JALRC_MMR6
    0U,	// JALRS16_MM
    0U,	// JALRS_MM
    0U,	// JALR_HB
    0U,	// JALR_HB64
    0U,	// JALR_MM
    0U,	// JALS_MM
    0U,	// JALX
    0U,	// JALX_MM
    0U,	// JAL_MM
    0U,	// JIALC
    0U,	// JIALC64
    0U,	// JIALC_MMR6
    0U,	// JIC
    0U,	// JIC64
    0U,	// JIC_MMR6
    0U,	// JR
    0U,	// JR16_MM
    0U,	// JR64
    0U,	// JRADDIUSP
    0U,	// JRC16_MM
    0U,	// JRC16_MMR6
    0U,	// JRCADDIUSP_MMR6
    0U,	// JR_HB
    0U,	// JR_HB64
    0U,	// JR_HB64_R6
    0U,	// JR_HB_R6
    0U,	// JR_MM
    0U,	// J_MM
    0U,	// Jal16
    0U,	// JalB16
    0U,	// JrRa16
    0U,	// JrcRa16
    0U,	// JrcRx16
    0U,	// JumpLinkReg16
    0U,	// LB
    0U,	// LB64
    0U,	// LBE
    0U,	// LBE_MM
    0U,	// LBU16_MM
    1U,	// LBUX
    1U,	// LBUX_MM
    0U,	// LBU_MMR6
    0U,	// LB_MM
    0U,	// LB_MMR6
    0U,	// LBu
    0U,	// LBu64
    0U,	// LBuE
    0U,	// LBuE_MM
    0U,	// LBu_MM
    0U,	// LD
    0U,	// LDC1
    0U,	// LDC164
    0U,	// LDC1_D64_MMR6
    0U,	// LDC1_MM_D32
    0U,	// LDC1_MM_D64
    0U,	// LDC2
    0U,	// LDC2_MMR6
    0U,	// LDC2_R6
    0U,	// LDC3
    0U,	// LDI_B
    0U,	// LDI_D
    0U,	// LDI_H
    0U,	// LDI_W
    0U,	// LDL
    0U,	// LDPC
    0U,	// LDR
    1U,	// LDXC1
    1U,	// LDXC164
    0U,	// LD_B
    0U,	// LD_D
    0U,	// LD_H
    0U,	// LD_W
    0U,	// LEA_ADDiu
    0U,	// LEA_ADDiu64
    0U,	// LEA_ADDiu_MM
    0U,	// LH
    0U,	// LH64
    0U,	// LHE
    0U,	// LHE_MM
    0U,	// LHU16_MM
    1U,	// LHX
    1U,	// LHX_MM
    0U,	// LH_MM
    0U,	// LHu
    0U,	// LHu64
    0U,	// LHuE
    0U,	// LHuE_MM
    0U,	// LHu_MM
    0U,	// LI16_MM
    0U,	// LI16_MMR6
    0U,	// LL
    0U,	// LL64
    0U,	// LL64_R6
    0U,	// LLD
    0U,	// LLD_R6
    0U,	// LLE
    0U,	// LLE_MM
    0U,	// LL_MM
    0U,	// LL_MMR6
    0U,	// LL_R6
    8324U,	// LSA
    1U,	// LSA_MMR6
    8324U,	// LSA_R6
    0U,	// LUI_MMR6
    1U,	// LUXC1
    1U,	// LUXC164
    1U,	// LUXC1_MM
    0U,	// LUi
    0U,	// LUi64
    0U,	// LUi_MM
    0U,	// LW
    0U,	// LW16_MM
    0U,	// LW64
    0U,	// LWC1
    0U,	// LWC1_MM
    0U,	// LWC2
    0U,	// LWC2_MMR6
    0U,	// LWC2_R6
    0U,	// LWC3
    0U,	// LWDSP
    0U,	// LWDSP_MM
    0U,	// LWE
    0U,	// LWE_MM
    0U,	// LWGP_MM
    0U,	// LWL
    0U,	// LWL64
    0U,	// LWLE
    0U,	// LWLE_MM
    0U,	// LWL_MM
    0U,	// LWM16_MM
    0U,	// LWM16_MMR6
    0U,	// LWM32_MM
    0U,	// LWPC
    0U,	// LWPC_MMR6
    0U,	// LWP_MM
    0U,	// LWR
    0U,	// LWR64
    0U,	// LWRE
    0U,	// LWRE_MM
    0U,	// LWR_MM
    0U,	// LWSP_MM
    0U,	// LWUPC
    0U,	// LWU_MM
    1U,	// LWX
    1U,	// LWXC1
    1U,	// LWXC1_MM
    1U,	// LWXS_MM
    1U,	// LWX_MM
    0U,	// LW_MM
    0U,	// LW_MMR6
    0U,	// LWu
    0U,	// LbRxRyOffMemX16
    0U,	// LbuRxRyOffMemX16
    0U,	// LhRxRyOffMemX16
    0U,	// LhuRxRyOffMemX16
    1U,	// LiRxImm16
    0U,	// LiRxImmAlignX16
    0U,	// LiRxImmX16
    1U,	// LwRxPcTcp16
    0U,	// LwRxPcTcpX16
    0U,	// LwRxRyOffMemX16
    0U,	// LwRxSpImmX16
    0U,	// MADD
    52U,	// MADDF_D
    52U,	// MADDF_D_MMR6
    52U,	// MADDF_S
    52U,	// MADDF_S_MMR6
    52U,	// MADDR_Q_H
    52U,	// MADDR_Q_W
    0U,	// MADDU
    4U,	// MADDU_DSP
    4U,	// MADDU_DSP_MM
    0U,	// MADDU_MM
    52U,	// MADDV_B
    52U,	// MADDV_D
    52U,	// MADDV_H
    52U,	// MADDV_W
    9348U,	// MADD_D32
    9348U,	// MADD_D32_MM
    9348U,	// MADD_D64
    4U,	// MADD_DSP
    4U,	// MADD_DSP_MM
    0U,	// MADD_MM
    52U,	// MADD_Q_H
    52U,	// MADD_Q_W
    9348U,	// MADD_S
    9348U,	// MADD_S_MM
    4U,	// MAQ_SA_W_PHL
    4U,	// MAQ_SA_W_PHL_MM
    4U,	// MAQ_SA_W_PHR
    4U,	// MAQ_SA_W_PHR_MM
    4U,	// MAQ_S_W_PHL
    4U,	// MAQ_S_W_PHL_MM
    4U,	// MAQ_S_W_PHR
    4U,	// MAQ_S_W_PHR_MM
    4U,	// MAXA_D
    4U,	// MAXA_D_MMR6
    4U,	// MAXA_S
    4U,	// MAXA_S_MMR6
    4U,	// MAXI_S_B
    4U,	// MAXI_S_D
    4U,	// MAXI_S_H
    4U,	// MAXI_S_W
    12U,	// MAXI_U_B
    12U,	// MAXI_U_D
    12U,	// MAXI_U_H
    12U,	// MAXI_U_W
    4U,	// MAX_A_B
    4U,	// MAX_A_D
    4U,	// MAX_A_H
    4U,	// MAX_A_W
    4U,	// MAX_D
    4U,	// MAX_D_MMR6
    4U,	// MAX_S
    4U,	// MAX_S_B
    4U,	// MAX_S_D
    4U,	// MAX_S_H
    4U,	// MAX_S_MMR6
    4U,	// MAX_S_W
    4U,	// MAX_U_B
    4U,	// MAX_U_D
    4U,	// MAX_U_H
    4U,	// MAX_U_W
    8U,	// MFC0
    8U,	// MFC0_MMR6
    0U,	// MFC1
    0U,	// MFC1_D64
    0U,	// MFC1_MM
    0U,	// MFC1_MMR6
    8U,	// MFC2
    0U,	// MFC2_MMR6
    8U,	// MFGC0
    8U,	// MFGC0_MM
    8U,	// MFHC0_MMR6
    0U,	// MFHC1_D32
    0U,	// MFHC1_D32_MM
    0U,	// MFHC1_D64
    0U,	// MFHC1_D64_MM
    0U,	// MFHC2_MMR6
    8U,	// MFHGC0
    8U,	// MFHGC0_MM
    0U,	// MFHI
    0U,	// MFHI16_MM
    0U,	// MFHI64
    0U,	// MFHI_DSP
    0U,	// MFHI_DSP_MM
    0U,	// MFHI_MM
    0U,	// MFLO
    0U,	// MFLO16_MM
    0U,	// MFLO64
    0U,	// MFLO_DSP
    0U,	// MFLO_DSP_MM
    0U,	// MFLO_MM
    18620U,	// MFTR
    4U,	// MINA_D
    4U,	// MINA_D_MMR6
    4U,	// MINA_S
    4U,	// MINA_S_MMR6
    4U,	// MINI_S_B
    4U,	// MINI_S_D
    4U,	// MINI_S_H
    4U,	// MINI_S_W
    12U,	// MINI_U_B
    12U,	// MINI_U_D
    12U,	// MINI_U_H
    12U,	// MINI_U_W
    4U,	// MIN_A_B
    4U,	// MIN_A_D
    4U,	// MIN_A_H
    4U,	// MIN_A_W
    4U,	// MIN_D
    4U,	// MIN_D_MMR6
    4U,	// MIN_S
    4U,	// MIN_S_B
    4U,	// MIN_S_D
    4U,	// MIN_S_H
    4U,	// MIN_S_MMR6
    4U,	// MIN_S_W
    4U,	// MIN_U_B
    4U,	// MIN_U_D
    4U,	// MIN_U_H
    4U,	// MIN_U_W
    4U,	// MOD
    4U,	// MODSUB
    4U,	// MODSUB_MM
    4U,	// MODU
    4U,	// MODU_MMR6
    4U,	// MOD_MMR6
    4U,	// MOD_S_B
    4U,	// MOD_S_D
    4U,	// MOD_S_H
    4U,	// MOD_S_W
    4U,	// MOD_U_B
    4U,	// MOD_U_D
    4U,	// MOD_U_H
    4U,	// MOD_U_W
    0U,	// MOVE16_MM
    0U,	// MOVE16_MMR6
    9348U,	// MOVEP_MM
    9348U,	// MOVEP_MMR6
    0U,	// MOVE_V
    4U,	// MOVF_D32
    4U,	// MOVF_D32_MM
    4U,	// MOVF_D64
    4U,	// MOVF_I
    4U,	// MOVF_I64
    4U,	// MOVF_I_MM
    4U,	// MOVF_S
    4U,	// MOVF_S_MM
    4U,	// MOVN_I64_D64
    4U,	// MOVN_I64_I
    4U,	// MOVN_I64_I64
    4U,	// MOVN_I64_S
    4U,	// MOVN_I_D32
    4U,	// MOVN_I_D32_MM
    4U,	// MOVN_I_D64
    4U,	// MOVN_I_I
    4U,	// MOVN_I_I64
    4U,	// MOVN_I_MM
    4U,	// MOVN_I_S
    4U,	// MOVN_I_S_MM
    4U,	// MOVT_D32
    4U,	// MOVT_D32_MM
    4U,	// MOVT_D64
    4U,	// MOVT_I
    4U,	// MOVT_I64
    4U,	// MOVT_I_MM
    4U,	// MOVT_S
    4U,	// MOVT_S_MM
    4U,	// MOVZ_I64_D64
    4U,	// MOVZ_I64_I
    4U,	// MOVZ_I64_I64
    4U,	// MOVZ_I64_S
    4U,	// MOVZ_I_D32
    4U,	// MOVZ_I_D32_MM
    4U,	// MOVZ_I_D64
    4U,	// MOVZ_I_I
    4U,	// MOVZ_I_I64
    4U,	// MOVZ_I_MM
    4U,	// MOVZ_I_S
    4U,	// MOVZ_I_S_MM
    0U,	// MSUB
    52U,	// MSUBF_D
    52U,	// MSUBF_D_MMR6
    52U,	// MSUBF_S
    52U,	// MSUBF_S_MMR6
    52U,	// MSUBR_Q_H
    52U,	// MSUBR_Q_W
    0U,	// MSUBU
    4U,	// MSUBU_DSP
    4U,	// MSUBU_DSP_MM
    0U,	// MSUBU_MM
    52U,	// MSUBV_B
    52U,	// MSUBV_D
    52U,	// MSUBV_H
    52U,	// MSUBV_W
    9348U,	// MSUB_D32
    9348U,	// MSUB_D32_MM
    9348U,	// MSUB_D64
    4U,	// MSUB_DSP
    4U,	// MSUB_DSP_MM
    0U,	// MSUB_MM
    52U,	// MSUB_Q_H
    52U,	// MSUB_Q_W
    9348U,	// MSUB_S
    9348U,	// MSUB_S_MM
    0U,	// MTC0
    0U,	// MTC0_MMR6
    0U,	// MTC1
    0U,	// MTC1_D64
    0U,	// MTC1_D64_MM
    0U,	// MTC1_MM
    0U,	// MTC1_MMR6
    0U,	// MTC2
    0U,	// MTC2_MMR6
    0U,	// MTGC0
    0U,	// MTGC0_MM
    0U,	// MTHC0_MMR6
    0U,	// MTHC1_D32
    0U,	// MTHC1_D32_MM
    0U,	// MTHC1_D64
    0U,	// MTHC1_D64_MM
    0U,	// MTHC2_MMR6
    0U,	// MTHGC0
    0U,	// MTHGC0_MM
    0U,	// MTHI
    0U,	// MTHI64
    0U,	// MTHI_DSP
    0U,	// MTHI_DSP_MM
    0U,	// MTHI_MM
    0U,	// MTHLIP
    0U,	// MTHLIP_MM
    0U,	// MTLO
    0U,	// MTLO64
    0U,	// MTLO_DSP
    0U,	// MTLO_DSP_MM
    0U,	// MTLO_MM
    0U,	// MTM0
    0U,	// MTM1
    0U,	// MTM2
    0U,	// MTP0
    0U,	// MTP1
    0U,	// MTP2
    2U,	// MTTR
    4U,	// MUH
    4U,	// MUHU
    4U,	// MUHU_MMR6
    4U,	// MUH_MMR6
    4U,	// MUL
    4U,	// MULEQ_S_W_PHL
    4U,	// MULEQ_S_W_PHL_MM
    4U,	// MULEQ_S_W_PHR
    4U,	// MULEQ_S_W_PHR_MM
    4U,	// MULEU_S_PH_QBL
    4U,	// MULEU_S_PH_QBL_MM
    4U,	// MULEU_S_PH_QBR
    4U,	// MULEU_S_PH_QBR_MM
    4U,	// MULQ_RS_PH
    4U,	// MULQ_RS_PH_MM
    4U,	// MULQ_RS_W
    4U,	// MULQ_RS_W_MMR2
    4U,	// MULQ_S_PH
    4U,	// MULQ_S_PH_MMR2
    4U,	// MULQ_S_W
    4U,	// MULQ_S_W_MMR2
    4U,	// MULR_PS64
    4U,	// MULR_Q_H
    4U,	// MULR_Q_W
    4U,	// MULSAQ_S_W_PH
    4U,	// MULSAQ_S_W_PH_MM
    4U,	// MULSA_W_PH
    4U,	// MULSA_W_PH_MMR2
    0U,	// MULT
    4U,	// MULTU_DSP
    4U,	// MULTU_DSP_MM
    4U,	// MULT_DSP
    4U,	// MULT_DSP_MM
    0U,	// MULT_MM
    0U,	// MULTu
    0U,	// MULTu_MM
    4U,	// MULU
    4U,	// MULU_MMR6
    4U,	// MULV_B
    4U,	// MULV_D
    4U,	// MULV_H
    4U,	// MULV_W
    4U,	// MUL_MM
    4U,	// MUL_MMR6
    4U,	// MUL_PH
    4U,	// MUL_PH_MMR2
    4U,	// MUL_Q_H
    4U,	// MUL_Q_W
    4U,	// MUL_R6
    4U,	// MUL_S_PH
    4U,	// MUL_S_PH_MMR2
    0U,	// Mfhi16
    0U,	// Mflo16
    0U,	// Move32R16
    0U,	// MoveR3216
    0U,	// NLOC_B
    0U,	// NLOC_D
    0U,	// NLOC_H
    0U,	// NLOC_W
    0U,	// NLZC_B
    0U,	// NLZC_D
    0U,	// NLZC_H
    0U,	// NLZC_W
    9348U,	// NMADD_D32
    9348U,	// NMADD_D32_MM
    9348U,	// NMADD_D64
    9348U,	// NMADD_S
    9348U,	// NMADD_S_MM
    9348U,	// NMSUB_D32
    9348U,	// NMSUB_D32_MM
    9348U,	// NMSUB_D64
    9348U,	// NMSUB_S
    9348U,	// NMSUB_S_MM
    4U,	// NOR
    4U,	// NOR64
    16U,	// NORI_B
    4U,	// NOR_MM
    4U,	// NOR_MMR6
    4U,	// NOR_V
    0U,	// NOT16_MM
    0U,	// NOT16_MMR6
    0U,	// NegRxRy16
    0U,	// NotRxRy16
    4U,	// OR
    0U,	// OR16_MM
    0U,	// OR16_MMR6
    4U,	// OR64
    16U,	// ORI_B
    20U,	// ORI_MMR6
    4U,	// OR_MM
    4U,	// OR_MMR6
    4U,	// OR_V
    20U,	// ORi
    20U,	// ORi64
    20U,	// ORi_MM
    0U,	// OrRxRxRy16
    4U,	// PACKRL_PH
    4U,	// PACKRL_PH_MM
    0U,	// PAUSE
    0U,	// PAUSE_MM
    0U,	// PAUSE_MMR6
    4U,	// PCKEV_B
    4U,	// PCKEV_D
    4U,	// PCKEV_H
    4U,	// PCKEV_W
    4U,	// PCKOD_B
    4U,	// PCKOD_D
    4U,	// PCKOD_H
    4U,	// PCKOD_W
    0U,	// PCNT_B
    0U,	// PCNT_D
    0U,	// PCNT_H
    0U,	// PCNT_W
    4U,	// PICK_PH
    4U,	// PICK_PH_MM
    4U,	// PICK_QB
    4U,	// PICK_QB_MM
    4U,	// PLL_PS64
    4U,	// PLU_PS64
    0U,	// POP
    0U,	// PRECEQU_PH_QBL
    0U,	// PRECEQU_PH_QBLA
    0U,	// PRECEQU_PH_QBLA_MM
    0U,	// PRECEQU_PH_QBL_MM
    0U,	// PRECEQU_PH_QBR
    0U,	// PRECEQU_PH_QBRA
    0U,	// PRECEQU_PH_QBRA_MM
    0U,	// PRECEQU_PH_QBR_MM
    0U,	// PRECEQ_W_PHL
    0U,	// PRECEQ_W_PHL_MM
    0U,	// PRECEQ_W_PHR
    0U,	// PRECEQ_W_PHR_MM
    0U,	// PRECEU_PH_QBL
    0U,	// PRECEU_PH_QBLA
    0U,	// PRECEU_PH_QBLA_MM
    0U,	// PRECEU_PH_QBL_MM
    0U,	// PRECEU_PH_QBR
    0U,	// PRECEU_PH_QBRA
    0U,	// PRECEU_PH_QBRA_MM
    0U,	// PRECEU_PH_QBR_MM
    4U,	// PRECRQU_S_QB_PH
    4U,	// PRECRQU_S_QB_PH_MM
    4U,	// PRECRQ_PH_W
    4U,	// PRECRQ_PH_W_MM
    4U,	// PRECRQ_QB_PH
    4U,	// PRECRQ_QB_PH_MM
    4U,	// PRECRQ_RS_PH_W
    4U,	// PRECRQ_RS_PH_W_MM
    4U,	// PRECR_QB_PH
    4U,	// PRECR_QB_PH_MMR2
    12U,	// PRECR_SRA_PH_W
    12U,	// PRECR_SRA_PH_W_MMR2
    12U,	// PRECR_SRA_R_PH_W
    12U,	// PRECR_SRA_R_PH_W_MMR2
    0U,	// PREF
    0U,	// PREFE
    0U,	// PREFE_MM
    0U,	// PREFX_MM
    0U,	// PREF_MM
    0U,	// PREF_MMR6
    0U,	// PREF_R6
    12U,	// PREPEND
    12U,	// PREPEND_MMR2
    4U,	// PUL_PS64
    4U,	// PUU_PS64
    0U,	// RADDU_W_QB
    0U,	// RADDU_W_QB_MM
    0U,	// RDDSP
    0U,	// RDDSP_MM
    16U,	// RDHWR
    16U,	// RDHWR64
    16U,	// RDHWR_MM
    8U,	// RDHWR_MMR6
    0U,	// RDPGPR_MMR6
    0U,	// RECIP_D32
    0U,	// RECIP_D32_MM
    0U,	// RECIP_D64
    0U,	// RECIP_D64_MM
    0U,	// RECIP_S
    0U,	// RECIP_S_MM
    0U,	// REPLV_PH
    0U,	// REPLV_PH_MM
    0U,	// REPLV_QB
    0U,	// REPLV_QB_MM
    0U,	// REPL_PH
    0U,	// REPL_PH_MM
    0U,	// REPL_QB
    0U,	// REPL_QB_MM
    0U,	// RINT_D
    0U,	// RINT_D_MMR6
    0U,	// RINT_S
    0U,	// RINT_S_MMR6
    12U,	// ROTR
    4U,	// ROTRV
    4U,	// ROTRV_MM
    12U,	// ROTR_MM
    0U,	// ROUND_L_D64
    0U,	// ROUND_L_D_MMR6
    0U,	// ROUND_L_S
    0U,	// ROUND_L_S_MMR6
    0U,	// ROUND_W_D32
    0U,	// ROUND_W_D64
    0U,	// ROUND_W_D_MMR6
    0U,	// ROUND_W_MM
    0U,	// ROUND_W_S
    0U,	// ROUND_W_S_MM
    0U,	// ROUND_W_S_MMR6
    0U,	// RSQRT_D32
    0U,	// RSQRT_D32_MM
    0U,	// RSQRT_D64
    0U,	// RSQRT_D64_MM
    0U,	// RSQRT_S
    0U,	// RSQRT_S_MM
    0U,	// Restore16
    0U,	// RestoreX16
    0U,	// SAA
    0U,	// SAAD
    8U,	// SAT_S_B
    28U,	// SAT_S_D
    32U,	// SAT_S_H
    12U,	// SAT_S_W
    8U,	// SAT_U_B
    28U,	// SAT_U_D
    32U,	// SAT_U_H
    12U,	// SAT_U_W
    0U,	// SB
    0U,	// SB16_MM
    0U,	// SB16_MMR6
    0U,	// SB64
    0U,	// SBE
    0U,	// SBE_MM
    0U,	// SB_MM
    0U,	// SB_MMR6
    0U,	// SC
    0U,	// SC64
    0U,	// SC64_R6
    0U,	// SCD
    0U,	// SCD_R6
    0U,	// SCE
    0U,	// SCE_MM
    0U,	// SC_MM
    0U,	// SC_MMR6
    0U,	// SC_R6
    0U,	// SD
    0U,	// SDBBP
    0U,	// SDBBP16_MM
    0U,	// SDBBP16_MMR6
    0U,	// SDBBP_MM
    0U,	// SDBBP_MMR6
    0U,	// SDBBP_R6
    0U,	// SDC1
    0U,	// SDC164
    0U,	// SDC1_D64_MMR6
    0U,	// SDC1_MM_D32
    0U,	// SDC1_MM_D64
    0U,	// SDC2
    0U,	// SDC2_MMR6
    0U,	// SDC2_R6
    0U,	// SDC3
    0U,	// SDIV
    0U,	// SDIV_MM
    0U,	// SDL
    0U,	// SDR
    1U,	// SDXC1
    1U,	// SDXC164
    0U,	// SEB
    0U,	// SEB64
    0U,	// SEB_MM
    0U,	// SEH
    0U,	// SEH64
    0U,	// SEH_MM
    4U,	// SELEQZ
    4U,	// SELEQZ64
    4U,	// SELEQZ_D
    4U,	// SELEQZ_D_MMR6
    4U,	// SELEQZ_MMR6
    4U,	// SELEQZ_S
    4U,	// SELEQZ_S_MMR6
    4U,	// SELNEZ
    4U,	// SELNEZ64
    4U,	// SELNEZ_D
    4U,	// SELNEZ_D_MMR6
    4U,	// SELNEZ_MMR6
    4U,	// SELNEZ_S
    4U,	// SELNEZ_S_MMR6
    52U,	// SEL_D
    52U,	// SEL_D_MMR6
    52U,	// SEL_S
    52U,	// SEL_S_MMR6
    4U,	// SEQ
    4U,	// SEQi
    0U,	// SH
    0U,	// SH16_MM
    0U,	// SH16_MMR6
    0U,	// SH64
    0U,	// SHE
    0U,	// SHE_MM
    16U,	// SHF_B
    16U,	// SHF_H
    16U,	// SHF_W
    0U,	// SHILO
    0U,	// SHILOV
    0U,	// SHILOV_MM
    0U,	// SHILO_MM
    4U,	// SHLLV_PH
    4U,	// SHLLV_PH_MM
    4U,	// SHLLV_QB
    4U,	// SHLLV_QB_MM
    4U,	// SHLLV_S_PH
    4U,	// SHLLV_S_PH_MM
    4U,	// SHLLV_S_W
    4U,	// SHLLV_S_W_MM
    32U,	// SHLL_PH
    32U,	// SHLL_PH_MM
    8U,	// SHLL_QB
    8U,	// SHLL_QB_MM
    32U,	// SHLL_S_PH
    32U,	// SHLL_S_PH_MM
    12U,	// SHLL_S_W
    12U,	// SHLL_S_W_MM
    4U,	// SHRAV_PH
    4U,	// SHRAV_PH_MM
    4U,	// SHRAV_QB
    4U,	// SHRAV_QB_MMR2
    4U,	// SHRAV_R_PH
    4U,	// SHRAV_R_PH_MM
    4U,	// SHRAV_R_QB
    4U,	// SHRAV_R_QB_MMR2
    4U,	// SHRAV_R_W
    4U,	// SHRAV_R_W_MM
    32U,	// SHRA_PH
    32U,	// SHRA_PH_MM
    8U,	// SHRA_QB
    8U,	// SHRA_QB_MMR2
    32U,	// SHRA_R_PH
    32U,	// SHRA_R_PH_MM
    8U,	// SHRA_R_QB
    8U,	// SHRA_R_QB_MMR2
    12U,	// SHRA_R_W
    12U,	// SHRA_R_W_MM
    4U,	// SHRLV_PH
    4U,	// SHRLV_PH_MMR2
    4U,	// SHRLV_QB
    4U,	// SHRLV_QB_MM
    32U,	// SHRL_PH
    32U,	// SHRL_PH_MMR2
    8U,	// SHRL_QB
    8U,	// SHRL_QB_MM
    0U,	// SH_MM
    0U,	// SH_MMR6
    0U,	// SIGRIE
    0U,	// SIGRIE_MMR6
    301U,	// SLDI_B
    73U,	// SLDI_D
    293U,	// SLDI_H
    77U,	// SLDI_W
    309U,	// SLD_B
    309U,	// SLD_D
    309U,	// SLD_H
    309U,	// SLD_W
    12U,	// SLL
    4U,	// SLL16_MM
    4U,	// SLL16_MMR6
    2U,	// SLL64_32
    2U,	// SLL64_64
    8U,	// SLLI_B
    28U,	// SLLI_D
    32U,	// SLLI_H
    12U,	// SLLI_W
    4U,	// SLLV
    4U,	// SLLV_MM
    4U,	// SLL_B
    4U,	// SLL_D
    4U,	// SLL_H
    12U,	// SLL_MM
    12U,	// SLL_MMR6
    4U,	// SLL_W
    4U,	// SLT
    4U,	// SLT64
    4U,	// SLT_MM
    4U,	// SLTi
    4U,	// SLTi64
    4U,	// SLTi_MM
    4U,	// SLTiu
    4U,	// SLTiu64
    4U,	// SLTiu_MM
    4U,	// SLTu
    4U,	// SLTu64
    4U,	// SLTu_MM
    4U,	// SNE
    4U,	// SNEi
    289U,	// SPLATI_B
    317U,	// SPLATI_D
    265U,	// SPLATI_H
    281U,	// SPLATI_W
    261U,	// SPLAT_B
    261U,	// SPLAT_D
    261U,	// SPLAT_H
    261U,	// SPLAT_W
    12U,	// SRA
    8U,	// SRAI_B
    28U,	// SRAI_D
    32U,	// SRAI_H
    12U,	// SRAI_W
    8U,	// SRARI_B
    28U,	// SRARI_D
    32U,	// SRARI_H
    12U,	// SRARI_W
    4U,	// SRAR_B
    4U,	// SRAR_D
    4U,	// SRAR_H
    4U,	// SRAR_W
    4U,	// SRAV
    4U,	// SRAV_MM
    4U,	// SRA_B
    4U,	// SRA_D
    4U,	// SRA_H
    12U,	// SRA_MM
    4U,	// SRA_W
    12U,	// SRL
    4U,	// SRL16_MM
    4U,	// SRL16_MMR6
    8U,	// SRLI_B
    28U,	// SRLI_D
    32U,	// SRLI_H
    12U,	// SRLI_W
    8U,	// SRLRI_B
    28U,	// SRLRI_D
    32U,	// SRLRI_H
    12U,	// SRLRI_W
    4U,	// SRLR_B
    4U,	// SRLR_D
    4U,	// SRLR_H
    4U,	// SRLR_W
    4U,	// SRLV
    4U,	// SRLV_MM
    4U,	// SRL_B
    4U,	// SRL_D
    4U,	// SRL_H
    12U,	// SRL_MM
    4U,	// SRL_W
    0U,	// SSNOP
    0U,	// SSNOP_MM
    0U,	// SSNOP_MMR6
    0U,	// ST_B
    0U,	// ST_D
    0U,	// ST_H
    0U,	// ST_W
    4U,	// SUB
    4U,	// SUBQH_PH
    4U,	// SUBQH_PH_MMR2
    4U,	// SUBQH_R_PH
    4U,	// SUBQH_R_PH_MMR2
    4U,	// SUBQH_R_W
    4U,	// SUBQH_R_W_MMR2
    4U,	// SUBQH_W
    4U,	// SUBQH_W_MMR2
    4U,	// SUBQ_PH
    4U,	// SUBQ_PH_MM
    4U,	// SUBQ_S_PH
    4U,	// SUBQ_S_PH_MM
    4U,	// SUBQ_S_W
    4U,	// SUBQ_S_W_MM
    4U,	// SUBSUS_U_B
    4U,	// SUBSUS_U_D
    4U,	// SUBSUS_U_H
    4U,	// SUBSUS_U_W
    4U,	// SUBSUU_S_B
    4U,	// SUBSUU_S_D
    4U,	// SUBSUU_S_H
    4U,	// SUBSUU_S_W
    4U,	// SUBS_S_B
    4U,	// SUBS_S_D
    4U,	// SUBS_S_H
    4U,	// SUBS_S_W
    4U,	// SUBS_U_B
    4U,	// SUBS_U_D
    4U,	// SUBS_U_H
    4U,	// SUBS_U_W
    4U,	// SUBU16_MM
    4U,	// SUBU16_MMR6
    4U,	// SUBUH_QB
    4U,	// SUBUH_QB_MMR2
    4U,	// SUBUH_R_QB
    4U,	// SUBUH_R_QB_MMR2
    4U,	// SUBU_MMR6
    4U,	// SUBU_PH
    4U,	// SUBU_PH_MMR2
    4U,	// SUBU_QB
    4U,	// SUBU_QB_MM
    4U,	// SUBU_S_PH
    4U,	// SUBU_S_PH_MMR2
    4U,	// SUBU_S_QB
    4U,	// SUBU_S_QB_MM
    12U,	// SUBVI_B
    12U,	// SUBVI_D
    12U,	// SUBVI_H
    12U,	// SUBVI_W
    4U,	// SUBV_B
    4U,	// SUBV_D
    4U,	// SUBV_H
    4U,	// SUBV_W
    4U,	// SUB_MM
    4U,	// SUB_MMR6
    4U,	// SUBu
    4U,	// SUBu_MM
    1U,	// SUXC1
    1U,	// SUXC164
    1U,	// SUXC1_MM
    0U,	// SW
    0U,	// SW16_MM
    0U,	// SW16_MMR6
    0U,	// SW64
    0U,	// SWC1
    0U,	// SWC1_MM
    0U,	// SWC2
    0U,	// SWC2_MMR6
    0U,	// SWC2_R6
    0U,	// SWC3
    0U,	// SWDSP
    0U,	// SWDSP_MM
    0U,	// SWE
    0U,	// SWE_MM
    0U,	// SWL
    0U,	// SWL64
    0U,	// SWLE
    0U,	// SWLE_MM
    0U,	// SWL_MM
    0U,	// SWM16_MM
    0U,	// SWM16_MMR6
    0U,	// SWM32_MM
    0U,	// SWP_MM
    0U,	// SWR
    0U,	// SWR64
    0U,	// SWRE
    0U,	// SWRE_MM
    0U,	// SWR_MM
    0U,	// SWSP_MM
    0U,	// SWSP_MMR6
    1U,	// SWXC1
    1U,	// SWXC1_MM
    0U,	// SW_MM
    0U,	// SW_MMR6
    0U,	// SYNC
    0U,	// SYNCI
    0U,	// SYNCI_MM
    0U,	// SYNCI_MMR6
    0U,	// SYNC_MM
    0U,	// SYNC_MMR6
    0U,	// SYSCALL
    0U,	// SYSCALL_MM
    0U,	// Save16
    0U,	// SaveX16
    0U,	// SbRxRyOffMemX16
    0U,	// SebRx16
    0U,	// SehRx16
    0U,	// ShRxRyOffMemX16
    12U,	// SllX16
    0U,	// SllvRxRy16
    0U,	// SltRxRy16
    1U,	// SltiRxImm16
    0U,	// SltiRxImmX16
    1U,	// SltiuRxImm16
    0U,	// SltiuRxImmX16
    0U,	// SltuRxRy16
    12U,	// SraX16
    0U,	// SravRxRy16
    12U,	// SrlX16
    0U,	// SrlvRxRy16
    4U,	// SubuRxRyRz16
    0U,	// SwRxRyOffMemX16
    0U,	// SwRxSpImmX16
    80U,	// TEQ
    0U,	// TEQI
    0U,	// TEQI_MM
    32U,	// TEQ_MM
    80U,	// TGE
    0U,	// TGEI
    0U,	// TGEIU
    0U,	// TGEIU_MM
    0U,	// TGEI_MM
    80U,	// TGEU
    32U,	// TGEU_MM
    32U,	// TGE_MM
    0U,	// TLBGINV
    0U,	// TLBGINVF
    0U,	// TLBGINVF_MM
    0U,	// TLBGINV_MM
    0U,	// TLBGP
    0U,	// TLBGP_MM
    0U,	// TLBGR
    0U,	// TLBGR_MM
    0U,	// TLBGWI
    0U,	// TLBGWI_MM
    0U,	// TLBGWR
    0U,	// TLBGWR_MM
    0U,	// TLBINV
    0U,	// TLBINVF
    0U,	// TLBINVF_MMR6
    0U,	// TLBINV_MMR6
    0U,	// TLBP
    0U,	// TLBP_MM
    0U,	// TLBR
    0U,	// TLBR_MM
    0U,	// TLBWI
    0U,	// TLBWI_MM
    0U,	// TLBWR
    0U,	// TLBWR_MM
    80U,	// TLT
    0U,	// TLTI
    0U,	// TLTIU_MM
    0U,	// TLTI_MM
    80U,	// TLTU
    32U,	// TLTU_MM
    32U,	// TLT_MM
    80U,	// TNE
    0U,	// TNEI
    0U,	// TNEI_MM
    32U,	// TNE_MM
    0U,	// TRUNC_L_D64
    0U,	// TRUNC_L_D_MMR6
    0U,	// TRUNC_L_S
    0U,	// TRUNC_L_S_MMR6
    0U,	// TRUNC_W_D32
    0U,	// TRUNC_W_D64
    0U,	// TRUNC_W_D_MMR6
    0U,	// TRUNC_W_MM
    0U,	// TRUNC_W_S
    0U,	// TRUNC_W_S_MM
    0U,	// TRUNC_W_S_MMR6
    0U,	// TTLTIU
    0U,	// UDIV
    0U,	// UDIV_MM
    4U,	// V3MULU
    4U,	// VMM0
    4U,	// VMULU
    52U,	// VSHF_B
    52U,	// VSHF_D
    52U,	// VSHF_H
    52U,	// VSHF_W
    0U,	// WAIT
    0U,	// WAIT_MM
    0U,	// WAIT_MMR6
    0U,	// WRDSP
    0U,	// WRDSP_MM
    0U,	// WRPGPR_MMR6
    0U,	// WSBH
    0U,	// WSBH_MM
    0U,	// WSBH_MMR6
    4U,	// XOR
    0U,	// XOR16_MM
    0U,	// XOR16_MMR6
    4U,	// XOR64
    16U,	// XORI_B
    20U,	// XORI_MMR6
    4U,	// XOR_MM
    4U,	// XOR_MMR6
    4U,	// XOR_V
    20U,	// XORi
    20U,	// XORi64
    20U,	// XORi_MM
    0U,	// XorRxRxRy16
    0U,	// YIELD
  };

  // Emit the opcode for the instruction.
  uint64_t Bits = 0;
  Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
  Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
  return {AsmStrs+(Bits & 16383)-1, Bits};

}
/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
LLVM_NO_PROFILE_INSTRUMENT_FUNCTION
void MipsInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) {
  O << "\t";

  auto MnemonicInfo = getMnemonic(MI);

  O << MnemonicInfo.first;

  uint64_t Bits = MnemonicInfo.second;
  assert(Bits != 0 && "Cannot print this instruction.");

  // Fragment 0 encoded into 5 bits for 17 unique commands.
  switch ((Bits >> 14) & 31) {
  default: llvm_unreachable("Invalid command number.");
  case 0:
    // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
    return;
    break;
  case 1:
    // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG...
    printOperand(MI, 0, STI, O);
    break;
  case 2:
    // B_MMR6_Pseudo, B_MM_Pseudo, B16_MM, BAL, BALC, BALC_MMR6, BC, BC16_MMR...
    printBranchOperand(MI, Address, 0, STI, O);
    break;
  case 3:
    // CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, MultRxRyRz1...
    printOperand(MI, 1, STI, O);
    O << ", ";
    break;
  case 4:
    // LWM_MM, SWM_MM, LWM16_MM, LWM16_MMR6, LWM32_MM, SWM16_MM, SWM16_MMR6, ...
    printRegisterList(MI, 0, STI, O);
    O << ", ";
    printMemOperand(MI, 1, STI, O);
    return;
    break;
  case 5:
    // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ...
    printOperand(MI, 3, STI, O);
    break;
  case 6:
    // AND16_MM, AND16_MMR6, LSA_MMR6, MTHC1_D32, MTHC1_D32_MM, MTHC1_D64, MT...
    printOperand(MI, 2, STI, O);
    O << ", ";
    break;
  case 7:
    // BREAK, BREAK_MM, BREAK_MMR6, HYPCALL, HYPCALL_MM, SDBBP_MM, SYSCALL_MM...
    printUImm<10>(MI, 0, STI, O);
    break;
  case 8:
    // BREAK16_MM, BREAK16_MMR6, SDBBP16_MM, SDBBP16_MMR6
    printUImm<4>(MI, 0, STI, O);
    return;
    break;
  case 9:
    // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,...
    printUImm<5>(MI, 2, STI, O);
    O << ", ";
    break;
  case 10:
    // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM
    printFCCOperand(MI, 2, STI, O);
    break;
  case 11:
    // J, JAL, JALS_MM, JALX, JALX_MM, JAL_MM, J_MM
    printJumpOperand(MI, 0, STI, O);
    return;
    break;
  case 12:
    // Jal16, JalB16
    printUImm<26>(MI, 0, STI, O);
    break;
  case 13:
    // SDBBP, SDBBP_MMR6, SDBBP_R6, SYSCALL
    printUImm<20>(MI, 0, STI, O);
    return;
    break;
  case 14:
    // SIGRIE, SIGRIE_MMR6
    printUImm<16>(MI, 0, STI, O);
    return;
    break;
  case 15:
    // SYNC, SYNC_MM, SYNC_MMR6
    printUImm<5>(MI, 0, STI, O);
    return;
    break;
  case 16:
    // SYNCI, SYNCI_MM, SYNCI_MMR6
    printMemOperand(MI, 0, STI, O);
    return;
    break;
  }


  // Fragment 1 encoded into 5 bits for 18 unique commands.
  switch ((Bits >> 19) & 31) {
  default: llvm_unreachable("Invalid command number.");
  case 0:
    // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG...
    O << ", ";
    break;
  case 1:
    // B_MMR6_Pseudo, B_MM_Pseudo, Constant32, JalOneReg, MFTDSP, MTTDSP, ADD...
    return;
    break;
  case 2:
    // CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, CTC1, CTC1_...
    printOperand(MI, 0, STI, O);
    break;
  case 3:
    // LwConstant32
    O << ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t";
    printOperand(MI, 1, STI, O);
    O << "\n2:";
    return;
    break;
  case 4:
    // MultRxRyRz16, MultuRxRyRz16, SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImm...
    printOperand(MI, 2, STI, O);
    break;
  case 5:
    // SelBeqZ, SelBneZ
    O << ", .+4\n\t\n\tmove ";
    printOperand(MI, 1, STI, O);
    O << ", ";
    printOperand(MI, 2, STI, O);
    return;
    break;
  case 6:
    // AND16_MM, AND16_MMR6, LSA_MMR6, OR16_MM, OR16_MMR6, PREFX_MM, XOR16_MM...
    printOperand(MI, 1, STI, O);
    break;
  case 7:
    // AddiuRxPcImmX16
    O << ", $pc, ";
    printOperand(MI, 1, STI, O);
    return;
    break;
  case 8:
    // AddiuSpImm16, Bimm16
    O << " # 16 bit inst";
    return;
    break;
  case 9:
    // Bteqz16, Btnez16
    O << "  # 16 bit inst";
    return;
    break;
  case 10:
    // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,...
    printMemOperand(MI, 0, STI, O);
    return;
    break;
  case 11:
    // FCMP_D32, FCMP_D32_MM, FCMP_D64
    O << ".d\t";
    printOperand(MI, 0, STI, O);
    O << ", ";
    printOperand(MI, 1, STI, O);
    return;
    break;
  case 12:
    // FCMP_S32, FCMP_S32_MM
    O << ".s\t";
    printOperand(MI, 0, STI, O);
    O << ", ";
    printOperand(MI, 1, STI, O);
    return;
    break;
  case 13:
    // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS...
    O << '[';
    break;
  case 14:
    // Jal16
    O << "\n\tnop";
    return;
    break;
  case 15:
    // JalB16
    O << "\t# branch\n\tnop";
    return;
    break;
  case 16:
    // SAA, SAAD
    O << ", (";
    printOperand(MI, 1, STI, O);
    O << ')';
    return;
    break;
  case 17:
    // SC, SC64, SC64_R6, SCD, SCD_R6, SCE, SCE_MM, SC_MM, SC_MMR6, SC_R6
    printMemOperand(MI, 2, STI, O);
    return;
    break;
  }


  // Fragment 2 encoded into 5 bits for 26 unique commands.
  switch ((Bits >> 24) & 31) {
  default: llvm_unreachable("Invalid command number.");
  case 0:
    // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG...
    printOperand(MI, 1, STI, O);
    break;
  case 1:
    // CTTC1, MTTACX, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, ADDIUS5_MM, AND16_...
    return;
    break;
  case 2:
    // GotPrologue16, AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B,...
    printOperand(MI, 2, STI, O);
    break;
  case 3:
    // LDMacro, LOAD_ACC128, LOAD_ACC64, LOAD_ACC64DSP, LOAD_CCOND_DSP, LoadA...
    printMemOperand(MI, 1, STI, O);
    return;
    break;
  case 4:
    // MTTC0, DMTC0, DMTC2, DMTGC0, FORK, LSA_MMR6, MTC0, MTC0_MMR6, MTC2, MT...
    O << ", ";
    break;
  case 5:
    // MultRxRyRz16, MultuRxRyRz16
    O << "\n\tmflo\t";
    printOperand(MI, 0, STI, O);
    return;
    break;
  case 6:
    // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt...
    printOperand(MI, 4, STI, O);
    break;
  case 7:
    // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz...
    O << "\n\tmove\t";
    printOperand(MI, 0, STI, O);
    O << ", $t8";
    return;
    break;
  case 8:
    // AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM
    printMemOperandEA(MI, 1, STI, O);
    return;
    break;
  case 9:
    // BBIT0, BBIT032, BBIT1, BBIT132
    printUImm<5>(MI, 1, STI, O);
    O << ", ";
    printBranchOperand(MI, Address, 2, STI, O);
    return;
    break;
  case 10:
    // BC1EQZ, BC1EQZC_MMR6, BC1F, BC1FL, BC1F_MM, BC1NEZ, BC1NEZC_MMR6, BC1T...
    printBranchOperand(MI, Address, 1, STI, O);
    break;
  case 11:
    // BREAK, BREAK_MM, BREAK_MMR6, RDDSP, WRDSP
    printUImm<10>(MI, 1, STI, O);
    return;
    break;
  case 12:
    // DMFC2_OCTEON, DMTC2_OCTEON, LUI_MMR6, LUi, LUi64, LUi_MM
    printUImm<16>(MI, 1, STI, O);
    return;
    break;
  case 13:
    // GINVT, GINVT_MMR6
    printUImm<2>(MI, 1, STI, O);
    return;
    break;
  case 14:
    // INSERT_B
    printUImm<4>(MI, 3, STI, O);
    O << "], ";
    printOperand(MI, 2, STI, O);
    return;
    break;
  case 15:
    // INSERT_D
    printUImm<1>(MI, 3, STI, O);
    O << "], ";
    printOperand(MI, 2, STI, O);
    return;
    break;
  case 16:
    // INSERT_H
    printUImm<3>(MI, 3, STI, O);
    O << "], ";
    printOperand(MI, 2, STI, O);
    return;
    break;
  case 17:
    // INSERT_W
    printUImm<2>(MI, 3, STI, O);
    O << "], ";
    printOperand(MI, 2, STI, O);
    return;
    break;
  case 18:
    // INSVE_B
    printUImm<4>(MI, 2, STI, O);
    O << "], ";
    printOperand(MI, 3, STI, O);
    O << '[';
    printUImm<0>(MI, 4, STI, O);
    O << ']';
    return;
    break;
  case 19:
    // INSVE_D
    printUImm<1>(MI, 2, STI, O);
    O << "], ";
    printOperand(MI, 3, STI, O);
    O << '[';
    printUImm<0>(MI, 4, STI, O);
    O << ']';
    return;
    break;
  case 20:
    // INSVE_H
    printUImm<3>(MI, 2, STI, O);
    O << "], ";
    printOperand(MI, 3, STI, O);
    O << '[';
    printUImm<0>(MI, 4, STI, O);
    O << ']';
    return;
    break;
  case 21:
    // INSVE_W
    printUImm<2>(MI, 2, STI, O);
    O << "], ";
    printOperand(MI, 3, STI, O);
    O << '[';
    printUImm<0>(MI, 4, STI, O);
    O << ']';
    return;
    break;
  case 22:
    // LWP_MM, SWP_MM
    printMemOperand(MI, 2, STI, O);
    return;
    break;
  case 23:
    // PREFX_MM
    O << '(';
    printOperand(MI, 0, STI, O);
    O << ')';
    return;
    break;
  case 24:
    // RDDSP_MM, WRDSP_MM
    printUImm<7>(MI, 1, STI, O);
    return;
    break;
  case 25:
    // REPL_QB, REPL_QB_MM
    printUImm<8>(MI, 1, STI, O);
    return;
    break;
  }


  // Fragment 3 encoded into 5 bits for 18 unique commands.
  switch ((Bits >> 29) & 31) {
  default: llvm_unreachable("Invalid command number.");
  case 0:
    // ABSMacro, CFTC1, JalTwoReg, LoadAddrImm32, LoadAddrImm64, LoadImm32, L...
    return;
    break;
  case 1:
    // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro...
    O << ", ";
    break;
  case 2:
    // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S...
    O << "\n\tbteqz\t";
    printBranchOperand(MI, Address, 2, STI, O);
    return;
    break;
  case 3:
    // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S...
    O << "\n\tbtnez\t";
    printBranchOperand(MI, Address, 2, STI, O);
    return;
    break;
  case 4:
    // GotPrologue16
    O << "\n\taddiu\t";
    printOperand(MI, 1, STI, O);
    O << ", $pc, ";
    printOperand(MI, 3, STI, O);
    O << "\n ";
    return;
    break;
  case 5:
    // MTTC0, DMTC0, DMTC2, DMTGC0, MTC0, MTC0_MMR6, MTC2, MTGC0, MTGC0_MM, M...
    printUImm<3>(MI, 2, STI, O);
    return;
    break;
  case 6:
    // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt...
    O << "\n\tbteqz\t.+4\n\tmove ";
    printOperand(MI, 1, STI, O);
    O << ", ";
    printOperand(MI, 2, STI, O);
    return;
    break;
  case 7:
    // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt...
    O << "\n\tbtnez\t.+4\n\tmove ";
    printOperand(MI, 1, STI, O);
    O << ", ";
    printOperand(MI, 2, STI, O);
    return;
    break;
  case 8:
    // AddiuRxRxImm16, LwRxPcTcp16
    O << "\t# 16 bit inst";
    return;
    break;
  case 9:
    // BeqzRxImm16, BnezRxImm16
    O << "  # 16 bit inst";
    return;
    break;
  case 10:
    // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ...
    O << '[';
    break;
  case 11:
    // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16
    O << " \t# 16 bit inst";
    return;
    break;
  case 12:
    // DSLL64_32
    O << ", 32";
    return;
    break;
  case 13:
    // FORK
    printOperand(MI, 2, STI, O);
    return;
    break;
  case 14:
    // LBUX, LBUX_MM, LDXC1, LDXC164, LHX, LHX_MM, LUXC1, LUXC164, LUXC1_MM, ...
    O << '(';
    printOperand(MI, 1, STI, O);
    O << ')';
    return;
    break;
  case 15:
    // LSA_MMR6
    printOperand(MI, 0, STI, O);
    O << ", ";
    printUImm<2, 1>(MI, 3, STI, O);
    return;
    break;
  case 16:
    // MTTR
    printUImm<1>(MI, 2, STI, O);
    O << ", ";
    printUImm<3>(MI, 3, STI, O);
    O << ", ";
    printUImm<1>(MI, 4, STI, O);
    return;
    break;
  case 17:
    // SLL64_32, SLL64_64
    O << ", 0";
    return;
    break;
  }


  // Fragment 4 encoded into 5 bits for 21 unique commands.
  switch ((Bits >> 34) & 31) {
  default: llvm_unreachable("Invalid command number.");
  case 0:
    // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro...
    printBranchOperand(MI, Address, 2, STI, O);
    return;
    break;
  case 1:
    // DMULImmMacro, DMULMacro, DMULOMacro, DMULOUMacro, DROL, DROLImm, DROR,...
    printOperand(MI, 2, STI, O);
    break;
  case 2:
    // MFTC0, BCLRI_B, BNEGI_B, BSETI_B, COPY_S_H, COPY_U_H, DMFC0, DMFC2, DM...
    printUImm<3>(MI, 2, STI, O);
    break;
  case 3:
    // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, APPEND, APPEND_MMR2, BCLRI_W, BNEG...
    printUImm<5>(MI, 2, STI, O);
    break;
  case 4:
    // ANDI_B, NORI_B, ORI_B, RDHWR, RDHWR64, RDHWR_MM, SHF_B, SHF_H, SHF_W, ...
    printUImm<8>(MI, 2, STI, O);
    return;
    break;
  case 5:
    // ANDI_MMR6, ANDi, ANDi64, ANDi_MM, AUI, AUI_MMR6, DAHI, DATI, DAUI, ORI...
    printUImm<16>(MI, 2, STI, O);
    return;
    break;
  case 6:
    // BALIGN, BALIGN_MMR2, COPY_S_W, COPY_U_W, SPLATI_W
    printUImm<2>(MI, 2, STI, O);
    break;
  case 7:
    // BCLRI_D, BNEGI_D, BSETI_D, DEXT, DEXT64_32, DINS, DROTR, DSLL, DSRA, D...
    printUImm<6>(MI, 2, STI, O);
    break;
  case 8:
    // BCLRI_H, BNEGI_H, BSETI_H, COPY_S_B, COPY_U_B, SAT_S_H, SAT_U_H, SHLL_...
    printUImm<4>(MI, 2, STI, O);
    break;
  case 9:
    // BINSLI_B, BINSRI_B, SLDI_H
    printUImm<3>(MI, 3, STI, O);
    break;
  case 10:
    // BINSLI_D, BINSRI_D
    printUImm<6>(MI, 3, STI, O);
    return;
    break;
  case 11:
    // BINSLI_H, BINSRI_H, SLDI_B
    printUImm<4>(MI, 3, STI, O);
    break;
  case 12:
    // BINSLI_W, BINSRI_W
    printUImm<5>(MI, 3, STI, O);
    return;
    break;
  case 13:
    // BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W...
    printOperand(MI, 3, STI, O);
    break;
  case 14:
    // BMNZI_B, BMZI_B, BSELI_B
    printUImm<8>(MI, 3, STI, O);
    return;
    break;
  case 15:
    // COPY_S_D, MFTR, SPLATI_D
    printUImm<1>(MI, 2, STI, O);
    break;
  case 16:
    // DEXTU, DINSU
    printUImm<5, 32>(MI, 2, STI, O);
    O << ", ";
    break;
  case 17:
    // FADD_S_MMR6, FDIV_S_MMR6, FMUL_S_MMR6, FSUB_S_MMR6
    printOperand(MI, 1, STI, O);
    return;
    break;
  case 18:
    // SLDI_D
    printUImm<1>(MI, 3, STI, O);
    O << ']';
    return;
    break;
  case 19:
    // SLDI_W
    printUImm<2>(MI, 3, STI, O);
    O << ']';
    return;
    break;
  case 20:
    // TEQ, TGE, TGEU, TLT, TLTU, TNE
    printUImm<10>(MI, 2, STI, O);
    return;
    break;
  }


  // Fragment 5 encoded into 3 bits for 5 unique commands.
  switch ((Bits >> 39) & 7) {
  default: llvm_unreachable("Invalid command number.");
  case 0:
    // DMULImmMacro, DMULMacro, DMULOMacro, DMULOUMacro, DROL, DROLImm, DROR,...
    return;
    break;
  case 1:
    // ALIGN, ALIGN_MMR6, CINS, CINS32, CINS64_32, CINS_i32, DALIGN, DEXT, DE...
    O << ", ";
    break;
  case 2:
    // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ...
    O << ']';
    return;
    break;
  case 3:
    // DEXTU
    printUImm<5, 1>(MI, 3, STI, O);
    return;
    break;
  case 4:
    // DINSU
    printUImm<6>(MI, 3, STI, O);
    return;
    break;
  }


  // Fragment 6 encoded into 4 bits for 10 unique commands.
  switch ((Bits >> 42) & 15) {
  default: llvm_unreachable("Invalid command number.");
  case 0:
    // ALIGN, ALIGN_MMR6
    printUImm<2>(MI, 3, STI, O);
    return;
    break;
  case 1:
    // CINS, CINS32, CINS64_32, CINS_i32, EXTS, EXTS32
    printUImm<5>(MI, 3, STI, O);
    return;
    break;
  case 2:
    // DALIGN, MFTR
    printUImm<3>(MI, 3, STI, O);
    break;
  case 3:
    // DEXT
    printUImm<6, 1>(MI, 3, STI, O);
    return;
    break;
  case 4:
    // DEXT64_32, EXT, EXT_MM, EXT_MMR6
    printUImm<5, 1>(MI, 3, STI, O);
    return;
    break;
  case 5:
    // DEXTM
    printUImm<5, 33>(MI, 3, STI, O);
    return;
    break;
  case 6:
    // DINS, INS, INS_MM, INS_MMR6
    printUImm<6>(MI, 3, STI, O);
    return;
    break;
  case 7:
    // DINSM
    printUImm<6, 2>(MI, 3, STI, O);
    return;
    break;
  case 8:
    // DLSA, DLSA_R6, LSA, LSA_R6
    printUImm<2, 1>(MI, 3, STI, O);
    return;
    break;
  case 9:
    // MADD_D32, MADD_D32_MM, MADD_D64, MADD_S, MADD_S_MM, MOVEP_MM, MOVEP_MM...
    printOperand(MI, 3, STI, O);
    return;
    break;
  }


  // Fragment 7 encoded into 1 bits for 2 unique commands.
  if ((Bits >> 46) & 1) {
    // MFTR
    O << ", ";
    printUImm<1>(MI, 4, STI, O);
    return;
  } else {
    // DALIGN
    return;
  }

}


/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description.  This returns the assembler name
/// for the specified register.
const char *MipsInstPrinter::getRegisterName(MCRegister Reg) {
  unsigned RegNo = Reg.id();
  assert(RegNo && RegNo < 442 && "Invalid register number!");


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
  static const char AsmStrs[] = {
  /* 0 */ "f10\0"
  /* 4 */ "w10\0"
  /* 8 */ "f20\0"
  /* 12 */ "DSPOutFlag20\0"
  /* 25 */ "w20\0"
  /* 29 */ "f30\0"
  /* 33 */ "w30\0"
  /* 37 */ "ac0\0"
  /* 41 */ "fcc0\0"
  /* 46 */ "f0\0"
  /* 49 */ "mpl0\0"
  /* 54 */ "p0\0"
  /* 57 */ "w0\0"
  /* 60 */ "f11\0"
  /* 64 */ "w11\0"
  /* 68 */ "f21\0"
  /* 72 */ "DSPOutFlag21\0"
  /* 85 */ "w21\0"
  /* 89 */ "f31\0"
  /* 93 */ "w31\0"
  /* 97 */ "ac1\0"
  /* 101 */ "fcc1\0"
  /* 106 */ "f1\0"
  /* 109 */ "mpl1\0"
  /* 114 */ "p1\0"
  /* 117 */ "w1\0"
  /* 120 */ "f12\0"
  /* 124 */ "w12\0"
  /* 128 */ "f22\0"
  /* 132 */ "DSPOutFlag22\0"
  /* 145 */ "w22\0"
  /* 149 */ "ac2\0"
  /* 153 */ "fcc2\0"
  /* 158 */ "f2\0"
  /* 161 */ "mpl2\0"
  /* 166 */ "p2\0"
  /* 169 */ "w2\0"
  /* 172 */ "f13\0"
  /* 176 */ "w13\0"
  /* 180 */ "f23\0"
  /* 184 */ "DSPOutFlag23\0"
  /* 197 */ "w23\0"
  /* 201 */ "ac3\0"
  /* 205 */ "fcc3\0"
  /* 210 */ "f3\0"
  /* 213 */ "w3\0"
  /* 216 */ "f14\0"
  /* 220 */ "w14\0"
  /* 224 */ "f24\0"
  /* 228 */ "w24\0"
  /* 232 */ "fcc4\0"
  /* 237 */ "f4\0"
  /* 240 */ "w4\0"
  /* 243 */ "f15\0"
  /* 247 */ "w15\0"
  /* 251 */ "f25\0"
  /* 255 */ "w25\0"
  /* 259 */ "fcc5\0"
  /* 264 */ "f5\0"
  /* 267 */ "w5\0"
  /* 270 */ "f16\0"
  /* 274 */ "w16\0"
  /* 278 */ "f26\0"
  /* 282 */ "w26\0"
  /* 286 */ "fcc6\0"
  /* 291 */ "f6\0"
  /* 294 */ "w6\0"
  /* 297 */ "f17\0"
  /* 301 */ "w17\0"
  /* 305 */ "f27\0"
  /* 309 */ "w27\0"
  /* 313 */ "fcc7\0"
  /* 318 */ "f7\0"
  /* 321 */ "w7\0"
  /* 324 */ "f18\0"
  /* 328 */ "w18\0"
  /* 332 */ "f28\0"
  /* 336 */ "w28\0"
  /* 340 */ "f8\0"
  /* 343 */ "w8\0"
  /* 346 */ "DSPOutFlag16_19\0"
  /* 362 */ "f19\0"
  /* 366 */ "w19\0"
  /* 370 */ "f29\0"
  /* 374 */ "w29\0"
  /* 378 */ "f9\0"
  /* 381 */ "w9\0"
  /* 384 */ "DSPEFI\0"
  /* 391 */ "ra\0"
  /* 394 */ "hwr_cc\0"
  /* 401 */ "pc\0"
  /* 404 */ "DSPCCond\0"
  /* 413 */ "DSPOutFlag\0"
  /* 424 */ "hi\0"
  /* 427 */ "hwr_cpunum\0"
  /* 438 */ "lo\0"
  /* 441 */ "zero\0"
  /* 446 */ "hwr_synci_step\0"
  /* 461 */ "fp\0"
  /* 464 */ "gp\0"
  /* 467 */ "sp\0"
  /* 470 */ "hwr_ccres\0"
  /* 480 */ "DSPPos\0"
  /* 487 */ "DSPSCount\0"
  /* 497 */ "DSPCarry\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

  static const uint16_t RegAsmOffset[] = {
    62, 404, 497, 384, 413, 480, 487, 461, 464, 122, 62, 2, 272, 218, 
    245, 174, 299, 401, 391, 467, 441, 218, 245, 272, 299, 37, 97, 149, 
    201, 62, 2, 62, 122, 174, 218, 245, 272, 299, 326, 360, 2, 62, 
    122, 174, 218, 245, 272, 299, 326, 360, 2, 62, 122, 174, 218, 245, 
    272, 299, 326, 360, 1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 
    9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, 1, 61, 
    121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 225, 252, 
    279, 306, 333, 371, 30, 90, 1, 61, 121, 173, 217, 244, 271, 298, 
    325, 359, 9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, 
    46, 158, 237, 291, 340, 0, 120, 216, 270, 324, 8, 128, 224, 278, 
    332, 29, 12, 72, 132, 184, 46, 106, 158, 210, 237, 264, 291, 318, 
    340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 362, 8, 68, 
    128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 41, 101, 153, 205, 
    232, 259, 286, 313, 2, 62, 122, 174, 218, 245, 272, 299, 326, 360, 
    1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 
    225, 252, 279, 306, 333, 371, 30, 90, 461, 46, 106, 158, 210, 237, 
    264, 291, 318, 340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 
    362, 8, 68, 128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 464, 
    37, 97, 149, 201, 427, 446, 394, 470, 218, 245, 272, 299, 326, 360, 
    1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 
    225, 252, 279, 306, 333, 371, 30, 90, 279, 306, 37, 97, 149, 201, 
    49, 109, 161, 326, 360, 1, 61, 121, 173, 217, 244, 271, 298, 325, 
    359, 9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, 54, 
    114, 166, 391, 271, 298, 325, 359, 9, 69, 129, 181, 467, 326, 360, 
    1, 61, 121, 173, 217, 244, 225, 252, 122, 174, 57, 117, 169, 213, 
    240, 267, 294, 321, 343, 381, 4, 64, 124, 176, 220, 247, 274, 301, 
    328, 366, 25, 85, 145, 197, 228, 255, 282, 309, 336, 374, 33, 93, 
    441, 218, 245, 272, 299, 37, 46, 106, 158, 210, 237, 264, 291, 318, 
    340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 362, 8, 68, 
    128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 346, 424, 279, 306, 
    438, 271, 298, 325, 359, 9, 69, 129, 181, 326, 360, 1, 61, 121, 
    173, 217, 244, 225, 252, 122, 174, 
  };

  assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&
          "Invalid alt name index for register!");
  return AsmStrs+RegAsmOffset[RegNo-1];
}

#ifdef PRINT_ALIAS_INSTR
#undef PRINT_ALIAS_INSTR

bool MipsInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) {
  static const PatternsForOpcode OpToPatterns[] = {
    {Mips::MFTACX, 0, 1 },
    {Mips::MFTC0, 1, 1 },
    {Mips::MFTHI, 2, 1 },
    {Mips::MFTLO, 3, 1 },
    {Mips::MTTACX, 4, 1 },
    {Mips::MTTC0, 5, 1 },
    {Mips::MTTHI, 6, 1 },
    {Mips::MTTLO, 7, 1 },
    {Mips::NORImm, 8, 1 },
    {Mips::NORImm64, 9, 1 },
    {Mips::SLTImm64, 10, 1 },
    {Mips::SLTUImm64, 11, 1 },
    {Mips::ADDIUPC, 12, 1 },
    {Mips::ADDIUPC_MMR6, 13, 1 },
    {Mips::ADDu, 14, 1 },
    {Mips::BC1F, 15, 1 },
    {Mips::BC1FL, 16, 1 },
    {Mips::BC1F_MM, 17, 1 },
    {Mips::BC1T, 18, 1 },
    {Mips::BC1TL, 19, 1 },
    {Mips::BC1T_MM, 20, 1 },
    {Mips::BEQL, 21, 1 },
    {Mips::BGEZAL, 22, 1 },
    {Mips::BGEZAL_MM, 23, 1 },
    {Mips::BNEL, 24, 1 },
    {Mips::BREAK, 25, 2 },
    {Mips::BREAK_MM, 27, 2 },
    {Mips::C_EQ_D32, 29, 1 },
    {Mips::C_EQ_D32_MM, 30, 1 },
    {Mips::C_EQ_D64, 31, 1 },
    {Mips::C_EQ_D64_MM, 32, 1 },
    {Mips::C_EQ_S, 33, 1 },
    {Mips::C_EQ_S_MM, 34, 1 },
    {Mips::C_F_D32, 35, 1 },
    {Mips::C_F_D32_MM, 36, 1 },
    {Mips::C_F_D64, 37, 1 },
    {Mips::C_F_D64_MM, 38, 1 },
    {Mips::C_F_S, 39, 1 },
    {Mips::C_F_S_MM, 40, 1 },
    {Mips::C_LE_D32, 41, 1 },
    {Mips::C_LE_D32_MM, 42, 1 },
    {Mips::C_LE_D64, 43, 1 },
    {Mips::C_LE_D64_MM, 44, 1 },
    {Mips::C_LE_S, 45, 1 },
    {Mips::C_LE_S_MM, 46, 1 },
    {Mips::C_LT_D32, 47, 1 },
    {Mips::C_LT_D32_MM, 48, 1 },
    {Mips::C_LT_D64, 49, 1 },
    {Mips::C_LT_D64_MM, 50, 1 },
    {Mips::C_LT_S, 51, 1 },
    {Mips::C_LT_S_MM, 52, 1 },
    {Mips::C_NGE_D32, 53, 1 },
    {Mips::C_NGE_D32_MM, 54, 1 },
    {Mips::C_NGE_D64, 55, 1 },
    {Mips::C_NGE_D64_MM, 56, 1 },
    {Mips::C_NGE_S, 57, 1 },
    {Mips::C_NGE_S_MM, 58, 1 },
    {Mips::C_NGLE_D32, 59, 1 },
    {Mips::C_NGLE_D32_MM, 60, 1 },
    {Mips::C_NGLE_D64, 61, 1 },
    {Mips::C_NGLE_D64_MM, 62, 1 },
    {Mips::C_NGLE_S, 63, 1 },
    {Mips::C_NGLE_S_MM, 64, 1 },
    {Mips::C_NGL_D32, 65, 1 },
    {Mips::C_NGL_D32_MM, 66, 1 },
    {Mips::C_NGL_D64, 67, 1 },
    {Mips::C_NGL_D64_MM, 68, 1 },
    {Mips::C_NGL_S, 69, 1 },
    {Mips::C_NGL_S_MM, 70, 1 },
    {Mips::C_NGT_D32, 71, 1 },
    {Mips::C_NGT_D32_MM, 72, 1 },
    {Mips::C_NGT_D64, 73, 1 },
    {Mips::C_NGT_D64_MM, 74, 1 },
    {Mips::C_NGT_S, 75, 1 },
    {Mips::C_NGT_S_MM, 76, 1 },
    {Mips::C_OLE_D32, 77, 1 },
    {Mips::C_OLE_D32_MM, 78, 1 },
    {Mips::C_OLE_D64, 79, 1 },
    {Mips::C_OLE_D64_MM, 80, 1 },
    {Mips::C_OLE_S, 81, 1 },
    {Mips::C_OLE_S_MM, 82, 1 },
    {Mips::C_OLT_D32, 83, 1 },
    {Mips::C_OLT_D32_MM, 84, 1 },
    {Mips::C_OLT_D64, 85, 1 },
    {Mips::C_OLT_D64_MM, 86, 1 },
    {Mips::C_OLT_S, 87, 1 },
    {Mips::C_OLT_S_MM, 88, 1 },
    {Mips::C_SEQ_D32, 89, 1 },
    {Mips::C_SEQ_D32_MM, 90, 1 },
    {Mips::C_SEQ_D64, 91, 1 },
    {Mips::C_SEQ_D64_MM, 92, 1 },
    {Mips::C_SEQ_S, 93, 1 },
    {Mips::C_SEQ_S_MM, 94, 1 },
    {Mips::C_SF_D32, 95, 1 },
    {Mips::C_SF_D32_MM, 96, 1 },
    {Mips::C_SF_D64, 97, 1 },
    {Mips::C_SF_D64_MM, 98, 1 },
    {Mips::C_SF_S, 99, 1 },
    {Mips::C_SF_S_MM, 100, 1 },
    {Mips::C_UEQ_D32, 101, 1 },
    {Mips::C_UEQ_D32_MM, 102, 1 },
    {Mips::C_UEQ_D64, 103, 1 },
    {Mips::C_UEQ_D64_MM, 104, 1 },
    {Mips::C_UEQ_S, 105, 1 },
    {Mips::C_UEQ_S_MM, 106, 1 },
    {Mips::C_ULE_D32, 107, 1 },
    {Mips::C_ULE_D32_MM, 108, 1 },
    {Mips::C_ULE_D64, 109, 1 },
    {Mips::C_ULE_D64_MM, 110, 1 },
    {Mips::C_ULE_S, 111, 1 },
    {Mips::C_ULE_S_MM, 112, 1 },
    {Mips::C_ULT_D32, 113, 1 },
    {Mips::C_ULT_D32_MM, 114, 1 },
    {Mips::C_ULT_D64, 115, 1 },
    {Mips::C_ULT_D64_MM, 116, 1 },
    {Mips::C_ULT_S, 117, 1 },
    {Mips::C_ULT_S_MM, 118, 1 },
    {Mips::C_UN_D32, 119, 1 },
    {Mips::C_UN_D32_MM, 120, 1 },
    {Mips::C_UN_D64, 121, 1 },
    {Mips::C_UN_D64_MM, 122, 1 },
    {Mips::C_UN_S, 123, 1 },
    {Mips::C_UN_S_MM, 124, 1 },
    {Mips::DADDu, 125, 1 },
    {Mips::DI, 126, 1 },
    {Mips::DIV, 127, 1 },
    {Mips::DIVU, 128, 1 },
    {Mips::DI_MM, 129, 1 },
    {Mips::DI_MMR6, 130, 1 },
    {Mips::DMT, 131, 1 },
    {Mips::DSUB, 132, 2 },
    {Mips::DSUBu, 134, 2 },
    {Mips::DVPE, 136, 1 },
    {Mips::EI, 137, 1 },
    {Mips::EI_MM, 138, 1 },
    {Mips::EI_MMR6, 139, 1 },
    {Mips::EMT, 140, 1 },
    {Mips::EVPE, 141, 1 },
    {Mips::HYPCALL, 142, 1 },
    {Mips::HYPCALL_MM, 143, 1 },
    {Mips::JALR, 144, 1 },
    {Mips::JALR64, 145, 1 },
    {Mips::JALRC_HB_MMR6, 146, 1 },
    {Mips::JALRC_MMR6, 147, 1 },
    {Mips::JALR_HB, 148, 1 },
    {Mips::JALR_HB64, 149, 1 },
    {Mips::JIALC, 150, 1 },
    {Mips::JIALC64, 151, 1 },
    {Mips::JIC, 152, 1 },
    {Mips::JIC64, 153, 1 },
    {Mips::MOVE16_MM, 154, 1 },
    {Mips::Move32R16, 155, 1 },
    {Mips::OR, 156, 1 },
    {Mips::OR64, 157, 1 },
    {Mips::RDHWR, 158, 1 },
    {Mips::RDHWR64, 159, 1 },
    {Mips::RDHWR_MM, 160, 1 },
    {Mips::RDHWR_MMR6, 161, 1 },
    {Mips::SDBBP, 162, 1 },
    {Mips::SDBBP_MMR6, 163, 1 },
    {Mips::SDBBP_R6, 164, 1 },
    {Mips::SIGRIE, 165, 1 },
    {Mips::SIGRIE_MMR6, 166, 1 },
    {Mips::SLL, 167, 1 },
    {Mips::SLL_MM, 168, 1 },
    {Mips::SLL_MMR6, 169, 1 },
    {Mips::SUB, 170, 2 },
    {Mips::SUBU_MMR6, 172, 2 },
    {Mips::SUB_MM, 174, 2 },
    {Mips::SUB_MMR6, 176, 2 },
    {Mips::SUBu, 178, 2 },
    {Mips::SUBu_MM, 180, 2 },
    {Mips::SWSP_MM, 182, 1 },
    {Mips::SYNC, 183, 1 },
    {Mips::SYNC_MM, 184, 1 },
    {Mips::SYNC_MMR6, 185, 1 },
    {Mips::SYSCALL, 186, 1 },
    {Mips::SYSCALL_MM, 187, 1 },
    {Mips::TEQ, 188, 1 },
    {Mips::TEQ_MM, 189, 1 },
    {Mips::TGE, 190, 1 },
    {Mips::TGEU, 191, 1 },
    {Mips::TGEU_MM, 192, 1 },
    {Mips::TGE_MM, 193, 1 },
    {Mips::TLT, 194, 1 },
    {Mips::TLTU, 195, 1 },
    {Mips::TLTU_MM, 196, 1 },
    {Mips::TLT_MM, 197, 1 },
    {Mips::TNE, 198, 1 },
    {Mips::TNE_MM, 199, 1 },
    {Mips::WAIT_MM, 200, 1 },
    {Mips::WRDSP, 201, 1 },
    {Mips::WRDSP_MM, 202, 1 },
    {Mips::YIELD, 203, 1 },
  };

  static const AliasPattern Patterns[] = {
    // Mips::MFTACX - 0
    {0, 0, 2, 4 },
    // Mips::MFTC0 - 1
    {10, 4, 3, 5 },
    // Mips::MFTHI - 2
    {23, 9, 2, 4 },
    // Mips::MFTLO - 3
    {32, 13, 2, 4 },
    // Mips::MTTACX - 4
    {41, 17, 2, 4 },
    // Mips::MTTC0 - 5
    {51, 21, 3, 5 },
    // Mips::MTTHI - 6
    {64, 26, 2, 4 },
    // Mips::MTTLO - 7
    {73, 30, 2, 4 },
    // Mips::NORImm - 8
    {82, 34, 3, 3 },
    // Mips::NORImm64 - 9
    {82, 37, 3, 3 },
    // Mips::SLTImm64 - 10
    {93, 40, 3, 3 },
    // Mips::SLTUImm64 - 11
    {104, 43, 3, 3 },
    // Mips::ADDIUPC - 12
    {116, 46, 2, 3 },
    // Mips::ADDIUPC_MMR6 - 13
    {116, 49, 2, 3 },
    // Mips::ADDu - 14
    {128, 52, 3, 6 },
    // Mips::BC1F - 15
    {140, 58, 2, 6 },
    // Mips::BC1FL - 16
    {150, 64, 2, 7 },
    // Mips::BC1F_MM - 17
    {140, 71, 2, 4 },
    // Mips::BC1T - 18
    {161, 75, 2, 6 },
    // Mips::BC1TL - 19
    {171, 81, 2, 7 },
    // Mips::BC1T_MM - 20
    {161, 88, 2, 4 },
    // Mips::BEQL - 21
    {182, 92, 3, 5 },
    // Mips::BGEZAL - 22
    {197, 97, 2, 5 },
    // Mips::BGEZAL_MM - 23
    {197, 102, 2, 3 },
    // Mips::BNEL - 24
    {206, 105, 3, 5 },
    // Mips::BREAK - 25
    {221, 110, 2, 4 },
    {227, 114, 2, 4 },
    // Mips::BREAK_MM - 27
    {221, 118, 2, 3 },
    {227, 121, 2, 3 },
    // Mips::C_EQ_D32 - 29
    {238, 124, 3, 9 },
    // Mips::C_EQ_D32_MM - 30
    {238, 133, 3, 7 },
    // Mips::C_EQ_D64 - 31
    {238, 140, 3, 9 },
    // Mips::C_EQ_D64_MM - 32
    {238, 149, 3, 7 },
    // Mips::C_EQ_S - 33
    {252, 156, 3, 8 },
    // Mips::C_EQ_S_MM - 34
    {252, 164, 3, 6 },
    // Mips::C_F_D32 - 35
    {266, 170, 3, 9 },
    // Mips::C_F_D32_MM - 36
    {266, 179, 3, 7 },
    // Mips::C_F_D64 - 37
    {266, 186, 3, 9 },
    // Mips::C_F_D64_MM - 38
    {266, 195, 3, 7 },
    // Mips::C_F_S - 39
    {279, 202, 3, 8 },
    // Mips::C_F_S_MM - 40
    {279, 210, 3, 6 },
    // Mips::C_LE_D32 - 41
    {292, 216, 3, 9 },
    // Mips::C_LE_D32_MM - 42
    {292, 225, 3, 7 },
    // Mips::C_LE_D64 - 43
    {292, 232, 3, 9 },
    // Mips::C_LE_D64_MM - 44
    {292, 241, 3, 7 },
    // Mips::C_LE_S - 45
    {306, 248, 3, 8 },
    // Mips::C_LE_S_MM - 46
    {306, 256, 3, 6 },
    // Mips::C_LT_D32 - 47
    {320, 262, 3, 9 },
    // Mips::C_LT_D32_MM - 48
    {320, 271, 3, 7 },
    // Mips::C_LT_D64 - 49
    {320, 278, 3, 9 },
    // Mips::C_LT_D64_MM - 50
    {320, 287, 3, 7 },
    // Mips::C_LT_S - 51
    {334, 294, 3, 8 },
    // Mips::C_LT_S_MM - 52
    {334, 302, 3, 6 },
    // Mips::C_NGE_D32 - 53
    {348, 308, 3, 9 },
    // Mips::C_NGE_D32_MM - 54
    {348, 317, 3, 7 },
    // Mips::C_NGE_D64 - 55
    {348, 324, 3, 9 },
    // Mips::C_NGE_D64_MM - 56
    {348, 333, 3, 7 },
    // Mips::C_NGE_S - 57
    {363, 340, 3, 8 },
    // Mips::C_NGE_S_MM - 58
    {363, 348, 3, 6 },
    // Mips::C_NGLE_D32 - 59
    {378, 354, 3, 9 },
    // Mips::C_NGLE_D32_MM - 60
    {378, 363, 3, 7 },
    // Mips::C_NGLE_D64 - 61
    {378, 370, 3, 9 },
    // Mips::C_NGLE_D64_MM - 62
    {378, 379, 3, 7 },
    // Mips::C_NGLE_S - 63
    {394, 386, 3, 8 },
    // Mips::C_NGLE_S_MM - 64
    {394, 394, 3, 6 },
    // Mips::C_NGL_D32 - 65
    {410, 400, 3, 9 },
    // Mips::C_NGL_D32_MM - 66
    {410, 409, 3, 7 },
    // Mips::C_NGL_D64 - 67
    {410, 416, 3, 9 },
    // Mips::C_NGL_D64_MM - 68
    {410, 425, 3, 7 },
    // Mips::C_NGL_S - 69
    {425, 432, 3, 8 },
    // Mips::C_NGL_S_MM - 70
    {425, 440, 3, 6 },
    // Mips::C_NGT_D32 - 71
    {440, 446, 3, 9 },
    // Mips::C_NGT_D32_MM - 72
    {440, 455, 3, 7 },
    // Mips::C_NGT_D64 - 73
    {440, 462, 3, 9 },
    // Mips::C_NGT_D64_MM - 74
    {440, 471, 3, 7 },
    // Mips::C_NGT_S - 75
    {455, 478, 3, 8 },
    // Mips::C_NGT_S_MM - 76
    {455, 486, 3, 6 },
    // Mips::C_OLE_D32 - 77
    {470, 492, 3, 9 },
    // Mips::C_OLE_D32_MM - 78
    {470, 501, 3, 7 },
    // Mips::C_OLE_D64 - 79
    {470, 508, 3, 9 },
    // Mips::C_OLE_D64_MM - 80
    {470, 517, 3, 7 },
    // Mips::C_OLE_S - 81
    {485, 524, 3, 8 },
    // Mips::C_OLE_S_MM - 82
    {485, 532, 3, 6 },
    // Mips::C_OLT_D32 - 83
    {500, 538, 3, 9 },
    // Mips::C_OLT_D32_MM - 84
    {500, 547, 3, 7 },
    // Mips::C_OLT_D64 - 85
    {500, 554, 3, 9 },
    // Mips::C_OLT_D64_MM - 86
    {500, 563, 3, 7 },
    // Mips::C_OLT_S - 87
    {515, 570, 3, 8 },
    // Mips::C_OLT_S_MM - 88
    {515, 578, 3, 6 },
    // Mips::C_SEQ_D32 - 89
    {530, 584, 3, 9 },
    // Mips::C_SEQ_D32_MM - 90
    {530, 593, 3, 7 },
    // Mips::C_SEQ_D64 - 91
    {530, 600, 3, 9 },
    // Mips::C_SEQ_D64_MM - 92
    {530, 609, 3, 7 },
    // Mips::C_SEQ_S - 93
    {545, 616, 3, 8 },
    // Mips::C_SEQ_S_MM - 94
    {545, 624, 3, 6 },
    // Mips::C_SF_D32 - 95
    {560, 630, 3, 9 },
    // Mips::C_SF_D32_MM - 96
    {560, 639, 3, 7 },
    // Mips::C_SF_D64 - 97
    {560, 646, 3, 9 },
    // Mips::C_SF_D64_MM - 98
    {560, 655, 3, 7 },
    // Mips::C_SF_S - 99
    {574, 662, 3, 8 },
    // Mips::C_SF_S_MM - 100
    {574, 670, 3, 6 },
    // Mips::C_UEQ_D32 - 101
    {588, 676, 3, 9 },
    // Mips::C_UEQ_D32_MM - 102
    {588, 685, 3, 7 },
    // Mips::C_UEQ_D64 - 103
    {588, 692, 3, 9 },
    // Mips::C_UEQ_D64_MM - 104
    {588, 701, 3, 7 },
    // Mips::C_UEQ_S - 105
    {603, 708, 3, 8 },
    // Mips::C_UEQ_S_MM - 106
    {603, 716, 3, 6 },
    // Mips::C_ULE_D32 - 107
    {618, 722, 3, 9 },
    // Mips::C_ULE_D32_MM - 108
    {618, 731, 3, 7 },
    // Mips::C_ULE_D64 - 109
    {618, 738, 3, 9 },
    // Mips::C_ULE_D64_MM - 110
    {618, 747, 3, 7 },
    // Mips::C_ULE_S - 111
    {633, 754, 3, 8 },
    // Mips::C_ULE_S_MM - 112
    {633, 762, 3, 6 },
    // Mips::C_ULT_D32 - 113
    {648, 768, 3, 9 },
    // Mips::C_ULT_D32_MM - 114
    {648, 777, 3, 7 },
    // Mips::C_ULT_D64 - 115
    {648, 784, 3, 9 },
    // Mips::C_ULT_D64_MM - 116
    {648, 793, 3, 7 },
    // Mips::C_ULT_S - 117
    {663, 800, 3, 8 },
    // Mips::C_ULT_S_MM - 118
    {663, 808, 3, 6 },
    // Mips::C_UN_D32 - 119
    {678, 814, 3, 9 },
    // Mips::C_UN_D32_MM - 120
    {678, 823, 3, 7 },
    // Mips::C_UN_D64 - 121
    {678, 830, 3, 9 },
    // Mips::C_UN_D64_MM - 122
    {678, 839, 3, 7 },
    // Mips::C_UN_S - 123
    {692, 846, 3, 8 },
    // Mips::C_UN_S_MM - 124
    {692, 854, 3, 6 },
    // Mips::DADDu - 125
    {128, 860, 3, 5 },
    // Mips::DI - 126
    {706, 865, 1, 4 },
    // Mips::DIV - 127
    {709, 869, 3, 5 },
    // Mips::DIVU - 128
    {720, 874, 3, 5 },
    // Mips::DI_MM - 129
    {706, 879, 1, 2 },
    // Mips::DI_MMR6 - 130
    {706, 881, 1, 3 },
    // Mips::DMT - 131
    {732, 884, 1, 3 },
    // Mips::DSUB - 132
    {736, 887, 3, 6 },
    {748, 893, 3, 6 },
    // Mips::DSUBu - 134
    {756, 899, 3, 6 },
    {769, 905, 3, 6 },
    // Mips::DVPE - 136
    {778, 911, 1, 3 },
    // Mips::EI - 137
    {783, 914, 1, 4 },
    // Mips::EI_MM - 138
    {783, 918, 1, 2 },
    // Mips::EI_MMR6 - 139
    {783, 920, 1, 3 },
    // Mips::EMT - 140
    {786, 923, 1, 3 },
    // Mips::EVPE - 141
    {790, 926, 1, 3 },
    // Mips::HYPCALL - 142
    {795, 929, 1, 5 },
    // Mips::HYPCALL_MM - 143
    {795, 934, 1, 4 },
    // Mips::JALR - 144
    {803, 938, 2, 6 },
    // Mips::JALR64 - 145
    {803, 944, 2, 4 },
    // Mips::JALRC_HB_MMR6 - 146
    {809, 948, 2, 4 },
    // Mips::JALRC_MMR6 - 147
    {821, 952, 2, 4 },
    // Mips::JALR_HB - 148
    {830, 956, 2, 5 },
    // Mips::JALR_HB64 - 149
    {830, 961, 2, 5 },
    // Mips::JIALC - 150
    {841, 966, 2, 6 },
    // Mips::JIALC64 - 151
    {841, 972, 2, 4 },
    // Mips::JIC - 152
    {850, 976, 2, 5 },
    // Mips::JIC64 - 153
    {850, 981, 2, 4 },
    // Mips::MOVE16_MM - 154
    {857, 985, 2, 3 },
    // Mips::Move32R16 - 155
    {857, 988, 2, 3 },
    // Mips::OR - 156
    {128, 991, 3, 6 },
    // Mips::OR64 - 157
    {128, 997, 3, 5 },
    // Mips::RDHWR - 158
    {861, 1002, 3, 5 },
    // Mips::RDHWR64 - 159
    {861, 1007, 3, 4 },
    // Mips::RDHWR_MM - 160
    {861, 1011, 3, 5 },
    // Mips::RDHWR_MMR6 - 161
    {861, 1016, 3, 5 },
    // Mips::SDBBP - 162
    {874, 1021, 1, 5 },
    // Mips::SDBBP_MMR6 - 163
    {874, 1026, 1, 3 },
    // Mips::SDBBP_R6 - 164
    {874, 1029, 1, 4 },
    // Mips::SIGRIE - 165
    {880, 1033, 1, 4 },
    // Mips::SIGRIE_MMR6 - 166
    {880, 1037, 1, 3 },
    // Mips::SLL - 167
    {857, 1040, 3, 5 },
    // Mips::SLL_MM - 168
    {857, 1045, 3, 4 },
    // Mips::SLL_MMR6 - 169
    {857, 1049, 3, 5 },
    // Mips::SUB - 170
    {887, 1054, 3, 5 },
    {898, 1059, 3, 5 },
    // Mips::SUBU_MMR6 - 172
    {905, 1064, 3, 5 },
    {917, 1069, 3, 5 },
    // Mips::SUB_MM - 174
    {887, 1074, 3, 5 },
    {898, 1079, 3, 5 },
    // Mips::SUB_MMR6 - 176
    {887, 1084, 3, 5 },
    {898, 1089, 3, 5 },
    // Mips::SUBu - 178
    {905, 1094, 3, 5 },
    {917, 1099, 3, 5 },
    // Mips::SUBu_MM - 180
    {905, 1104, 3, 5 },
    {917, 1109, 3, 5 },
    // Mips::SWSP_MM - 182
    {925, 1114, 3, 2 },
    // Mips::SYNC - 183
    {937, 1116, 1, 4 },
    // Mips::SYNC_MM - 184
    {937, 1120, 1, 2 },
    // Mips::SYNC_MMR6 - 185
    {937, 1122, 1, 3 },
    // Mips::SYSCALL - 186
    {942, 1125, 1, 3 },
    // Mips::SYSCALL_MM - 187
    {942, 1128, 1, 2 },
    // Mips::TEQ - 188
    {950, 1130, 3, 6 },
    // Mips::TEQ_MM - 189
    {950, 1136, 3, 4 },
    // Mips::TGE - 190
    {961, 1140, 3, 6 },
    // Mips::TGEU - 191
    {972, 1146, 3, 6 },
    // Mips::TGEU_MM - 192
    {972, 1152, 3, 4 },
    // Mips::TGE_MM - 193
    {961, 1156, 3, 4 },
    // Mips::TLT - 194
    {984, 1160, 3, 6 },
    // Mips::TLTU - 195
    {995, 1166, 3, 6 },
    // Mips::TLTU_MM - 196
    {995, 1172, 3, 4 },
    // Mips::TLT_MM - 197
    {984, 1176, 3, 4 },
    // Mips::TNE - 198
    {1007, 1180, 3, 6 },
    // Mips::TNE_MM - 199
    {1007, 1186, 3, 4 },
    // Mips::WAIT_MM - 200
    {1018, 1190, 1, 2 },
    // Mips::WRDSP - 201
    {1023, 1192, 2, 4 },
    // Mips::WRDSP_MM - 202
    {1023, 1196, 2, 4 },
    // Mips::YIELD - 203
    {1032, 1200, 2, 4 },
  };

  static const AliasPatternCond Conds[] = {
    // (MFTACX GPR32Opnd:$rt, AC0) - 0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::AC0},
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0) - 4
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::COP0RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (MFTHI GPR32Opnd:$rt, AC0) - 9
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::AC0},
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (MFTLO GPR32Opnd:$rt, AC0) - 13
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::AC0},
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (MTTACX AC0, GPR32Opnd:$rt) - 17
    {AliasPatternCond::K_Reg, Mips::AC0},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0) - 21
    {AliasPatternCond::K_RegClass, Mips::COP0RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (MTTHI AC0, GPR32Opnd:$rt) - 26
    {AliasPatternCond::K_Reg, Mips::AC0},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (MTTLO AC0, GPR32Opnd:$rt) - 30
    {AliasPatternCond::K_Reg, Mips::AC0},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm) - 34
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_TiedReg, 0},
    {AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit},
    // (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 37
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_TiedReg, 0},
    {AliasPatternCond::K_Feature, Mips::FeatureGP64Bit},
    // (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 40
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_TiedReg, 0},
    {AliasPatternCond::K_Feature, Mips::FeatureGP64Bit},
    // (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 43
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_TiedReg, 0},
    {AliasPatternCond::K_Feature, Mips::FeatureGP64Bit},
    // (ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm) - 46
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm) - 49
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 52
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (BC1F FCC0, brtarget:$offset) - 58
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (BC1FL FCC0, brtarget:$offset) - 64
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (BC1F_MM FCC0, brtarget:$offset) - 71
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (BC1T FCC0, brtarget:$offset) - 75
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (BC1TL FCC0, brtarget:$offset) - 81
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (BC1T_MM FCC0, brtarget:$offset) - 88
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 92
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (BGEZAL ZERO, brtarget:$offset) - 97
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (BGEZAL_MM ZERO, brtarget_mm:$offset) - 102
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    // (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 105
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (BREAK 0, 0) - 110
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (BREAK uimm10:$imm, 0) - 114
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (BREAK_MM 0, 0) - 118
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (BREAK_MM uimm10:$imm, 0) - 121
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (C_EQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 124
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_EQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 133
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_EQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 140
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_EQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 149
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_EQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 156
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_EQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 164
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_F_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 170
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_F_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 179
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_F_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 186
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_F_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 195
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_F_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 202
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_F_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 210
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_LE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 216
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_LE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 225
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_LE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 232
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_LE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 241
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_LE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 248
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_LE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 256
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_LT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 262
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_LT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 271
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_LT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 278
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_LT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 287
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_LT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 294
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_LT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 302
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_NGE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 308
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_NGE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 317
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_NGE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 324
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_NGE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 333
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_NGE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 340
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_NGE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 348
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_NGLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 354
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_NGLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 363
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_NGLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 370
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_NGLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 379
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_NGLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 386
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_NGLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 394
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_NGL_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 400
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_NGL_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 409
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_NGL_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 416
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_NGL_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 425
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_NGL_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 432
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_NGL_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 440
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_NGT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 446
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_NGT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 455
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_NGT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 462
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_NGT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 471
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_NGT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 478
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_NGT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 486
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_OLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 492
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_OLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 501
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_OLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 508
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_OLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 517
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_OLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 524
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_OLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 532
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_OLT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 538
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_OLT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 547
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_OLT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 554
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_OLT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 563
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_OLT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 570
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_OLT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 578
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_SEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 584
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_SEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 593
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_SEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 600
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_SEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 609
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_SEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 616
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_SEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 624
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_SF_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 630
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_SF_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 639
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_SF_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 646
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_SF_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 655
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_SF_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 662
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_SF_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 670
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_UEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 676
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_UEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 685
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_UEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 692
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_UEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 701
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_UEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 708
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_UEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 716
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_ULE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 722
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_ULE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 731
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_ULE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 738
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_ULE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 747
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_ULE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 754
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_ULE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 762
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_ULT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 768
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_ULT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 777
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_ULT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 784
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_ULT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 793
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_ULT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 800
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_ULT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 808
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_UN_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 814
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_UN_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 823
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_UN_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 830
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_UN_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 839
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (C_UN_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 846
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (C_UN_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 854
    {AliasPatternCond::K_Reg, Mips::FCC0},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
    // (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 860
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO_64},
    {AliasPatternCond::K_Feature, Mips::FeatureGP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (DI ZERO) - 865
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r2},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (DIV GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 869
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_TiedReg, 0},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 874
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_TiedReg, 0},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (DI_MM ZERO) - 879
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (DI_MMR6 ZERO) - 881
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (DMT ZERO) - 884
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 887
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO_64},
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips3},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 893
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO_64},
    {AliasPatternCond::K_TiedReg, 0},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips3},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 899
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO_64},
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips3},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 905
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO_64},
    {AliasPatternCond::K_TiedReg, 0},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips3},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (DVPE ZERO) - 911
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (EI ZERO) - 914
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r2},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (EI_MM ZERO) - 918
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (EI_MMR6 ZERO) - 920
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (EMT ZERO) - 923
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (EVPE ZERO) - 926
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (HYPCALL 0) - 929
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r5},
    {AliasPatternCond::K_Feature, Mips::FeatureVirt},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (HYPCALL_MM 0) - 934
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r5},
    {AliasPatternCond::K_Feature, Mips::FeatureVirt},
    // (JALR ZERO, GPR32Opnd:$rs) - 938
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (JALR64 ZERO_64, GPR64Opnd:$rs) - 944
    {AliasPatternCond::K_Reg, Mips::ZERO_64},
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips64r6},
    // (JALRC_HB_MMR6 RA, GPR32Opnd:$rs) - 948
    {AliasPatternCond::K_Reg, Mips::RA},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (JALRC_MMR6 RA, GPR32Opnd:$rs) - 952
    {AliasPatternCond::K_Reg, Mips::RA},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (JALR_HB RA, GPR32Opnd:$rs) - 956
    {AliasPatternCond::K_Reg, Mips::RA},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (JALR_HB64 RA_64, GPR64Opnd:$rs) - 961
    {AliasPatternCond::K_Reg, Mips::RA_64},
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips64},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (JIALC GPR32Opnd:$rs, 0) - 966
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (JIALC64 GPR64Opnd:$rs, 0) - 972
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips64r6},
    // (JIC GPR32Opnd:$rs, 0) - 976
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (JIC64 GPR64Opnd:$rs, 0) - 981
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips64r6},
    // (MOVE16_MM ZERO, ZERO) - 985
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (Move32R16 ZERO, S0) - 988
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Reg, Mips::S0},
    {AliasPatternCond::K_Feature, Mips::FeatureMips16},
    // (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 991
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 997
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO_64},
    {AliasPatternCond::K_Feature, Mips::FeatureGP64Bit},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (RDHWR GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1002
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0) - 1007
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
    {AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureGP64Bit},
    // (RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1011
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    // (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1016
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (SDBBP 0) - 1021
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
    // (SDBBP_MMR6 0) - 1026
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (SDBBP_R6 0) - 1029
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (SIGRIE 0) - 1033
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (SIGRIE_MMR6 0) - 1037
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (SLL ZERO, ZERO, 0) - 1040
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (SLL_MM ZERO, ZERO, 0) - 1045
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (SLL_MMR6 ZERO, ZERO, 0) - 1049
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1054
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1059
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_TiedReg, 0},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1064
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1069
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_TiedReg, 0},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1074
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1079
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_TiedReg, 0},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1084
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1089
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_TiedReg, 0},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1094
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1099
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_TiedReg, 0},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1104
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1109
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_TiedReg, 0},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
    // (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset) - 1114
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (SYNC 0) - 1116
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (SYNC_MM 0) - 1120
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (SYNC_MMR6 0) - 1122
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
    // (SYSCALL 0) - 1125
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (SYSCALL_MM 0) - 1128
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1130
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1136
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1140
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1146
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1152
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1156
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1160
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1166
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1172
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1176
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1180
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1186
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (WAIT_MM 0) - 1190
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (WRDSP GPR32Opnd:$rt, 31) - 1192
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(31)},
    {AliasPatternCond::K_Feature, Mips::FeatureDSP},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
    // (WRDSP_MM GPR32Opnd:$rt, 31) - 1196
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Imm, uint32_t(31)},
    {AliasPatternCond::K_Feature, Mips::FeatureDSP},
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
    // (YIELD ZERO, GPR32Opnd:$rs) - 1200
    {AliasPatternCond::K_Reg, Mips::ZERO},
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
  };

  static const char AsmStrings[] =
    /* 0 */ "mftacx $\x01\0"
    /* 10 */ "mftc0 $\x01, $\x02\0"
    /* 23 */ "mfthi $\x01\0"
    /* 32 */ "mftlo $\x01\0"
    /* 41 */ "mttacx $\x02\0"
    /* 51 */ "mttc0 $\x02, $\x01\0"
    /* 64 */ "mtthi $\x02\0"
    /* 73 */ "mttlo $\x02\0"
    /* 82 */ "nor	$\x01, $\x03\0"
    /* 93 */ "slt	$\x01, $\x03\0"
    /* 104 */ "sltu	$\x01, $\x03\0"
    /* 116 */ "lapc $\x01, $\x02\0"
    /* 128 */ "move $\x01, $\x02\0"
    /* 140 */ "bc1f $\xFF\x02\x01\0"
    /* 150 */ "bc1fl $\xFF\x02\x01\0"
    /* 161 */ "bc1t $\xFF\x02\x01\0"
    /* 171 */ "bc1tl $\xFF\x02\x01\0"
    /* 182 */ "beqzl $\x01, $\xFF\x03\x01\0"
    /* 197 */ "bal $\xFF\x02\x01\0"
    /* 206 */ "bnezl $\x01, $\xFF\x03\x01\0"
    /* 221 */ "break\0"
    /* 227 */ "break $\xFF\x01\x02\0"
    /* 238 */ "c.eq.d $\x02, $\x03\0"
    /* 252 */ "c.eq.s $\x02, $\x03\0"
    /* 266 */ "c.f.d $\x02, $\x03\0"
    /* 279 */ "c.f.s $\x02, $\x03\0"
    /* 292 */ "c.le.d $\x02, $\x03\0"
    /* 306 */ "c.le.s $\x02, $\x03\0"
    /* 320 */ "c.lt.d $\x02, $\x03\0"
    /* 334 */ "c.lt.s $\x02, $\x03\0"
    /* 348 */ "c.nge.d $\x02, $\x03\0"
    /* 363 */ "c.nge.s $\x02, $\x03\0"
    /* 378 */ "c.ngle.d $\x02, $\x03\0"
    /* 394 */ "c.ngle.s $\x02, $\x03\0"
    /* 410 */ "c.ngl.d $\x02, $\x03\0"
    /* 425 */ "c.ngl.s $\x02, $\x03\0"
    /* 440 */ "c.ngt.d $\x02, $\x03\0"
    /* 455 */ "c.ngt.s $\x02, $\x03\0"
    /* 470 */ "c.ole.d $\x02, $\x03\0"
    /* 485 */ "c.ole.s $\x02, $\x03\0"
    /* 500 */ "c.olt.d $\x02, $\x03\0"
    /* 515 */ "c.olt.s $\x02, $\x03\0"
    /* 530 */ "c.seq.d $\x02, $\x03\0"
    /* 545 */ "c.seq.s $\x02, $\x03\0"
    /* 560 */ "c.sf.d $\x02, $\x03\0"
    /* 574 */ "c.sf.s $\x02, $\x03\0"
    /* 588 */ "c.ueq.d $\x02, $\x03\0"
    /* 603 */ "c.ueq.s $\x02, $\x03\0"
    /* 618 */ "c.ule.d $\x02, $\x03\0"
    /* 633 */ "c.ule.s $\x02, $\x03\0"
    /* 648 */ "c.ult.d $\x02, $\x03\0"
    /* 663 */ "c.ult.s $\x02, $\x03\0"
    /* 678 */ "c.un.d $\x02, $\x03\0"
    /* 692 */ "c.un.s $\x02, $\x03\0"
    /* 706 */ "di\0"
    /* 709 */ "div $\x01, $\x03\0"
    /* 720 */ "divu $\x01, $\x03\0"
    /* 732 */ "dmt\0"
    /* 736 */ "dneg $\x01, $\x03\0"
    /* 748 */ "dneg $\x01\0"
    /* 756 */ "dnegu $\x01, $\x03\0"
    /* 769 */ "dnegu $\x01\0"
    /* 778 */ "dvpe\0"
    /* 783 */ "ei\0"
    /* 786 */ "emt\0"
    /* 790 */ "evpe\0"
    /* 795 */ "hypcall\0"
    /* 803 */ "jr $\x02\0"
    /* 809 */ "jalrc.hb $\x02\0"
    /* 821 */ "jalrc $\x02\0"
    /* 830 */ "jalr.hb $\x02\0"
    /* 841 */ "jalrc $\x01\0"
    /* 850 */ "jrc $\x01\0"
    /* 857 */ "nop\0"
    /* 861 */ "rdhwr $\x01, $\x02\0"
    /* 874 */ "sdbbp\0"
    /* 880 */ "sigrie\0"
    /* 887 */ "neg $\x01, $\x03\0"
    /* 898 */ "neg $\x01\0"
    /* 905 */ "negu $\x01, $\x03\0"
    /* 917 */ "negu $\x01\0"
    /* 925 */ "sw $\x01, $\xFF\x02\x03\0"
    /* 937 */ "sync\0"
    /* 942 */ "syscall\0"
    /* 950 */ "teq $\x01, $\x02\0"
    /* 961 */ "tge $\x01, $\x02\0"
    /* 972 */ "tgeu $\x01, $\x02\0"
    /* 984 */ "tlt $\x01, $\x02\0"
    /* 995 */ "tltu $\x01, $\x02\0"
    /* 1007 */ "tne $\x01, $\x02\0"
    /* 1018 */ "wait\0"
    /* 1023 */ "wrdsp $\x01\0"
    /* 1032 */ "yield $\x02\0"
  ;

#ifndef NDEBUG
  static struct SortCheck {
    SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
      assert(std::is_sorted(
                 OpToPatterns.begin(), OpToPatterns.end(),
                 [](const PatternsForOpcode &L, const PatternsForOpcode &R) {
                   return L.Opcode < R.Opcode;
                 }) &&
             "tablegen failed to sort opcode patterns");
    }
  } sortCheckVar(OpToPatterns);
#endif

  AliasMatchingData M {
    ArrayRef(OpToPatterns),
    ArrayRef(Patterns),
    ArrayRef(Conds),
    StringRef(AsmStrings, std::size(AsmStrings)),
    nullptr,
  };
  const char *AsmString = matchAliasPatterns(MI, &STI, M);
  if (!AsmString) return false;

  unsigned I = 0;
  while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
         AsmString[I] != '$' && AsmString[I] != '\0')
    ++I;
  OS << '\t' << StringRef(AsmString, I);
  if (AsmString[I] != '\0') {
    if (AsmString[I] == ' ' || AsmString[I] == '\t') {
      OS << '\t';
      ++I;
    }
    do {
      if (AsmString[I] == '$') {
        ++I;
        if (AsmString[I] == (char)0xff) {
          ++I;
          int OpIdx = AsmString[I++] - 1;
          int PrintMethodIdx = AsmString[I++] - 1;
          printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, OS);
        } else
          printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS);
      } else {
        OS << AsmString[I++];
      }
    } while (AsmString[I] != '\0');
  }

  return true;
}

void MipsInstPrinter::printCustomAliasOperand(
         const MCInst *MI, uint64_t Address, unsigned OpIdx,
         unsigned PrintMethodIdx,
         const MCSubtargetInfo &STI,
         raw_ostream &OS) {
  switch (PrintMethodIdx) {
  default:
    llvm_unreachable("Unknown PrintMethod kind");
    break;
  case 0:
    printBranchOperand(MI, Address, OpIdx, STI, OS);
    break;
  case 1:
    printUImm<10>(MI, OpIdx, STI, OS);
    break;
  case 2:
    printMemOperand(MI, OpIdx, STI, OS);
    break;
  }
}

#endif // PRINT_ALIAS_INSTR